Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Alliance Semiconductor Co., Ltd.

Petrochina Company Limited

Sichuan Shengnuo Oil. and Gas Engineering Technology Service Co., Ltd

Weilin Wang

Yingbing Guan

Mengchen Yang

Jiin Lai

Jing Chen

Xiaoyang Li

Xiaoliang Kang

Yang Shi

Zhenhua Huang

Lei Yi

Long Cheng

Juanli Song

Peng Shen

Yue Qin

Shuai Zhang

Zhongmin Chen

Xianpei Zheng

Fan Yang

Chen Chen

Yan Huang

Lei Huang

Wei Zhou

Ting Ting Zhang

Jiangbo Wang

Xinyu Gao

Huiyun Ma

Yankui Niu

Jinglong Liu

Yongfeng Song

Xuemin Zhang

Chunhui Zheng

Xueqiang Wang

Hao Tan

Changqing Ye

Hanbing Tang

Daogang Cai

Zonghao Dong

Yukui Hong

Yun Miao

Fengjing Sun

Minfang Zhu

The present invention relates to a method for a processor and a computer system to enter system management mode (SMM). The method is applied to the processor, which includes at least one logical core. The method includes entering the SMM in response to a system management interrupt (SMI), storing current state information to a corresponding state save area; setting operation mode to target operating mode, and executing the SMI handler under the target operating mode. The address of the state save area, the address of the core configuration information memory space, and the address of the SMI handler can be determined directly. Each logical core may enter the target operating mode directly through hardware setting every time after entering the SMM, and thus does not need to perform a fixed operation of mode switching when executing the SMI handler, which may improve the execution efficiency of the SMI handler.

Method for entering system management mode, processor, and computer system

An instruction simulation device and a method thereof are provided. The instruction simulation device includes a processor. The processor includes an instruction decoder which generates format information of a ready-for-execution instruction. The processor determines whether the ready-for-execution instruction currently executed by the processor is a compatible instruction or an extended instruction based on the format information of the ready-for-execution instruction. If the ready-for-execution instruction is an extended instruction under the new instruction set or the extended instruction set, the processor converts the ready-for-execution instruction into a simulation program corresponding to the extended instruction, and simulates an execution result of the ready-for-execution instruction by executing the simulation program. The simulation program is composed of at least one compatible instructions of the processor. If the ready-for-execution instruction is a compatible instruction, the processor executes the ready-for-execution instruction.

Instruction simulation device and method thereof

A processor and a method for designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data are shown. In response to an instruction that is in the instruction set architecture and is executed to designate a designated-level cache within the current core as a target to perform writing-back and invalidation, a decoder of the current core outputs microinstructions. According to the microinstructions, a level-designation request indicating the designated-level cache within the current core is transferred to the hierarchical cache system through the memory order buffer. In response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the current core, writes modified cache lines (which are obtained from the recognized cache lines) back to the system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.

Processor and method designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data

A technology flushing a hierarchical cache structure based on a designated key identification code and a designated address. A processor includes a first core and a last level cache (LLC). The first core includes a decoder, a memory ordering buffer, and a first in-core cache module. In response to an Instruction Set Architecture (ISA) instruction that requests to flush a hierarchical cache structure according to a designated key identification code and a designated address, the decoder outputs at least one microinstruction. According to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then the first in-core cache module provides the LLC with the flushing request, so that the LLC flushes its matching cache line which matches the designated key identification code and the designated address.

Processor, computer system, and method for flushing hierarchical cache structure based on a designated key identification code and a designated address

A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back, in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one direct invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each direct invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

Computing system with direct invalidation in a hierarchical cache structure based on at least one designated key identification code

A processor and a method for designating a demotion target to demote the demotion target from an in-core cache structure to an out-of-core cache structure is shown. In response to a cache data demotion instruction supported by an instruction set architecture, a first core of a processor operates a decoder to decode the cache data demotion instruction into microinstructions. According to the microinstructions, a demotion target designation request is transferred to a last-level cache (LLC) through a memory order buffer to drive the LLC to query an out-of-core cache table. According to the demotion target's cache status in the first core obtained from the out-of-core cache table, the LLC outputs a snoop request to the first core to snoop on the demotion target and demote the demotion target from the in-core cache structure of the first core to the LLC.

Processor and method for designating a demotion target to be demoted from an in-core cache structure to an out-of-core cache structure

An instruction execution method for a microprocessor is provided. The microprocessor includes a model specific register (MSR). And, the instruction execution method includes the following steps. A target instruction is received using an instruction cache. The target instruction is decoded using an instruction translator to determine whether the target instruction is a specific instruction is a specific instruction. When the target instruction is the specific instruction, a model specific register index of the target instruction is obtained to directly read or write the model specific register.

Instruction execution method and instruction execution device

An instruction configuration and execution method includes the following steps. A target instruction is received through an instruction cache. The target instruction is decoded by an instruction translator. It is determined whether the target instruction has the authority to read or write the model specific register in an unprivileged state. It is determined whether the model specific register index of the specific instruction corresponds to a specific model specific register, so as to order the microprocessor to perform an instruction serialization operation.

A interconnect system, including a plurality of sockets and a first interconnect interface. Any two of the sockets are accessible to each other's hardware resources by transmitting a first packet and a second packet through the first interconnect interface. The first packet includes first interconnect information, used for establishing communication between the two sockets. The second packet includes a first data payload, loaded from one of the two sockets. The sockets include a first socket and a second socket, configured to be interconnected with each other through the first interconnect interface.

Interconnect system

A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction.

Method and system for executing new instructions

The present invention discloses a permanent packer and an extended gas lift method using the permanent packer, the method comprising: S1. imbedding the extended gas lift embedded pipe when setting the permanent packer, wherein the extended gas lift embedded pipe has an upper end being closed and a lower end being open, is provided therein with a one-way valve through which the fluid can pass from top to bottom; S2. lowering a breaking device from the production casing when in the extended gas lift, to break the upper end of the extended gas lift embedded pipe such that the upper and lower ends of the extended gas lift embedded pipe are communicated; and S3. injecting gas into the production casing, lifting the accumulated liquid in the bottom hole to the ground surface, to complete the extended gas lift. The method does not affect the sealing property of the permanent packer, can fully adapt to the demand in the early and middle stages of gas well development, and meanwhile can realize extended gas lift without workover in the middle and later stages of gas well development, and has low implementation cost and good safety.

Permanent packer and extended gas lift method using permanent packer

A computing system with a first instruction of an instruction set architecture (ISA) for write-back and invalidation in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for write-back and invalidation in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one write-back and invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each write-back and invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

Computing system with write-back and invalidation in a hierarchical cache structure based on at least one designated key identification code

A technology for flushing a translation lookaside buffer (TLB) according to a designated key identification code (designated key ID). An instruction of an instruction set architecture is proposed to flush the TLB according to the designated key ID. A decoder transforms the instruction into at least one microinstruction. According to a flushing microinstruction included in the at least one microinstruction, a designated key ID is supplied to a control logic circuit of the TLB through a memory order buffer, so that the control logic circuit flushes matched entries in the TLB, wherein the matched entries match the designated key ID.

Processor and method for flushing translation lookaside buffer according to designated key identification code

An interconnect interface is applied between sockets or between dies. The interconnect interface includes a first transmitter (TX), a first receiver (RX), and an electrical physical layer (EPHY) coupled between the first TX and the first RX. The data provided by a first device is transmitted from the first TX to the EPHY and then received by the first RX to be retrieved by a second device. The first TX includes an arbiter for arbitrating between a plurality of channels of the first device to obtain data from the first device. The first TX includes a packet generator, which packs the data obtained from the first device into a packet to be transmitted through the EPHY. The first TX further includes a first buffer that backs up the data obtained from the first device for retransmission.

Interconnect interface

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Beijing, China

Weilin Wang