Intel Corporation

Weiliang Lin

Shu Xu

Tianyou Li

Junyong Ding

Jinkui Ren

Yongnian Le

Kangyuan Shu

Xuefeng Deng

Chaobo Zhu

Yaojie Yan

Zidong Jiang

Yong Hu

Xiaokang Qin

In one example, a system for executing applications can include a main processor to initialize a virtual machine to execute an application. The main processor can also determine a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture. Additionally, the main processor can transmit an instruction from the application to the auxiliary processor for execution and update context data for the application in response to receiving an execution result from the auxiliary processor.

Executing an application with multiple processors

Roller skate

Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.

Dynamic code execution location in heterogeneous memory

Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.

Hybrid rendering systems and methods

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Shanghai, China

Weiliang Lin