Yangtze Memory Technologies Co., Ltd.

Weijun Wan

Yue Sheng

Jianjie Li

Chunyuan Hou

Ke Jiang

Shu Xie

Yu Wang

ZhiChao Du

A memory device, a memory system, and a method for data calculation with the memory device are provided. The memory device includes an array of memory cells and a peripheral circuit coupled to the memory cells is provided. The peripheral circuit includes page buffers configured to store first data transmitted from a data interface of the memory device and to sense second data from the array of memory cells. The peripheral circuit further includes at least one process unit coupled to the page buffers via a data-path bus of the peripheral circuit and configured to perform calculation based on the first data and the second data. The peripheral circuit further includes a control logic configured to program the second data into the array of memory cells.

Memory device, memory system, and method for data calculation with the memory device

In an aspect, a memory device includes page buffers and a controller coupled to the page buffers. Each of the page buffers includes N data latches configured to store data, where N is a positive integer. The controller is configured to receive data that includes data units, wherein each of the data units includes N bits, store the data units in the N data latches, convert the data stored in the N data latches based on a table, and program cells of the memory device based on the converted data. The table include N rows and 2columns of bits. Bits from column 2+2 to column 2in Nrow of the table are identical.

Data preprocessing (DPP) pattern supporting both normal program and early cache release program (ECRP)

An operating method for a memory, a memory, and a memory system are provided in the present application. The memory includes at least a plurality of word lines and a plurality of strings, and the plurality of word lines include a target word line, and each word line is coupled to a plurality of strings. Each string includes a plurality of memory cells. In accordance with the operating method provided by the present application, the first verification and the second verification are performed on a plurality of target memory cells with first and second verify voltages during performing a first programming operation on a plurality of target memory cells in target string coupled to the target word line, and the second start program voltage is determined based on at least the second verification result, ensuring the accuracy of the second start program voltage.

Operating method for a memory, a memory, and a memory system to improve programming efficiency

A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSG), and suspending programming or verifying of the memory cell in a suspend phase.

Memory device and operating method thereof

In certain aspects, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. At least one of the memory cells is set to one of 2levels corresponding to a piece of N-bits data, where Nis an integer greater than 1. The peripheral circuit is configured to apply a first program voltage to a select row of the memory cells, perform a first verification of the select row of the memory cells at a last level of the 2levels after applying the first program voltage, perform a first verify fail count (VFC) based on a result of the first verification and a first VFC criterion, apply a second program voltage greater than the first program voltage to the select row of the memory cells after performing the first VFC, and perform a second VFC based on the result of the first verification and a second VFC criterion different from the first VFC criterion within a period of applying the second program voltage.

Memory device and program operation thereof

In one aspect, a page buffer includes a first latch configured to store program verification information; a second latch configured to store first bit line forced information; and a dynamic latch configured to store second bit line forced information. The first bit line forced information is different from the second bit line forced information. The dynamic latch includes a control switch coupled to the second latch. And the dynamic latch is configured to store information through a capacitor to which the control switch is coupled.

Page buffer supporting different bit line forcing operations using a dynamic latch

A peripheral circuit of a memory device includes page buffers. Each page buffer includes a main latch, a bias latch, (N−1) data latches, and a cache latch coupled to a data path. The peripheral circuit is further configured to: in the process of programming a first physical page, disable a bit line bias function to release the bias latch to replace one of N page latches to perform a programming verification of memory states; release one of the N page latches to cache program data of one of the N logical pages of a second physical page; and in the process of programming the first physical page, store the program data of the one of the N logical pages of the second physical page in a released page latch.

Memory device, memory system, and method of operating the same

A peripheral circuit of a memory device is configured to: in the process of programming a first physical page, perform a programming verification to a programming corresponding to the 2th memory state; when the program verification of the 2th memory state is passed, identifiers corresponding to the 1st to 2th memory states stored by the main latch are made different from those corresponding to the 2+1st to 2th memory states; release at least one of the N page latches to cache program data of at least one logical page of the N logical pages of a second physical page; and the programming data of one logical page in the N logical pages of the second physical page is stored in a released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N−2).

Disclosed herein are memory device, method for data preprocessing of program operations. In an aspect, a memory device comprises N data latches configured to store data and a controller coupled to the N data latches. The controller is configured to receive the data that includes data units and store the data units in the N data latches, wherein each of the data units includes N bits. The processor is further configured to convert the data units based on a first table and a second table and program cells of the memory device based on the converted data units. The first and the second tables include N rows and 2columns of bits and bits from column 2+2 to column 2in Nrow of the second table are identical.

A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data.

Architecture and method for NAND memory programming

The present disclosure provides a three-dimensional NAND memory device, comprising a first NAND string including a first channel corresponding to a first cell to be inhibited to program, and a controller configured to control a word line driver and a bit line driver to do the following operations: prior to applying a program voltage to a selected word line, charging a first bit line electrically coupling with the first channel to a first voltage level for charging the first channel to the first voltage level, charging an array common source electrically coupling with the first bit line for further charging the first channel to a second voltage level higher than the first voltage level, and cutting off the electrical coupling between the first bit line and the first channel for preparing to apply the program voltage to the selected word line.

Methods of reducing program disturb by array source coupling in 3D NAND memory devices

In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows, bit lines respectively coupled to the columns, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row based on a current data page. Each memory cell is configured to store a piece of N-bits data at one of 2levels, where N is an integer greater than 1. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, one multipurpose storage unit, and N&#x2212;1 data storage units.

Memory device with page buffer circuit and program operation thereof

In a method of programming a memory device, inhibit information is stored to first latch structures and second latch structures. A first state programming voltage is applied to data lines of memory cells of the memory device to program the memory cells to the first state. A first state verification voltage is applied to the data lines of the memory cells to perform a first state verification operation on the memory cells. The first state verification operation verifies first state threshold voltages of the memory cells based on a first target value and also generates failure pattern data of the first state verification operation. The failure pattern data is then stored to the second latch structures. Further, a first level adjusted verification voltage is applied to the data lines of a portion of the memory cells that fails the first level verification operation to perform a first level adjusted verification operation.

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Wuhan, China

Weijun Wan