Cavium, Inc.

Google Inc.

Marvell Asia Pte., Ltd.

Broadcom Corporation

Xpliant, Inc.

Cavium International

Weihuang Wang

Prashant R Chandra

Srinivas Vaduvatha

Srinath Atluri

Gerald Schmidt

Tsahi Daniel

Jiazhen Zheng

Weinan Ma

Abhishek Agarwal

Premshanth Theivendran

Mohan Balan

Weiwei Jiang

Shrikant Sundaram Lnu

Jeffrey T Huynh

Sowmya Hotha

Hugh McEvoy Walsh

Enrique Musoll

Chien-Hsien Wu

Nimalan Siva

Saurabh Shrivastava

Nikhil Jayakumar

Srinath Alturi

Guy Hutchison

Anh T Tran

Nandita Dukkipati

Chirinjeev Singh

Zubin Shah

Xiaoming Wang

Daman Ahluwalia

Mohammad Kamel Issa

Michael Roger Marty

Gurushankar Rajamani

Saurin Patel

Dan Tu

Gautam Kumar

Yuliang Li

Hassan Wassel

Hassan Mohamed Gamal Hassan Wassel

Nicholas McDonald

Neelesh Bansod

Masoud Moshref Javadi

Prasanna Vetrivel

Ajay Venkatesan

Behnam Montazeri

Hugh Mcevoy Walsh

Nicholas Mcdonald

A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.

Efficient hash table lookup

A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including a reorder engine and a retransmission engine may be utilized for the reliable transport of the packets. The content addressable memory module includes a primary CAM that may be logically partitioned into a plurality of physical sub-CAMs. One or more processors are in communication with the content addressable memory module. The one or more processors receive a set of data packets. A lookup operation is performed by the one or more processors to access data entries stored in each of the sub-content addressable memories. An update operation is performed by the one or more processors at a selected sub-content addressable memory from the plurality of the sub-content addressable memories.

High bandwidth content addressable memory (CAM) based hardware architecture for datacenter networking

Aspects of the disclosure are directed to a high performance connection scheduler for reliable transport protocols in data center networking. The connection scheduler can handle enqueue events, dequeue events, and update events. The connection scheduler can include a connection queue, scheduling queue, and quality of service arbiter to support scheduling a large number of connections at a high rate.

High performance connection scheduler

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Hierarchical statisically multiplexed counters and a method thereof

Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.

Method and apparatus for flexible and efficient analytics in a network switch

A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.

Packet cache system and method

The technology is directed to the use of a bitmap generated at a receiver to track the status of received packets sent by a transmitter. The technology may include a network device including an input port, output port, and circuitry. The circuitry may generate a transmitter bitmap that tracks each data packet sent to another network device. The circuitry of the network device may receive, from the other network device, a receiver bitmap that identifies each data packet that is received and not received from the network device. The circuitry may then determine which data packets to retransmit by comparing the transmitter bitmap to the receiver bitmap.

Early retransmission for hardware reliable transport

An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.

Off-chip memory backed reliable transport connection cache hardware architecture

A communication technology that provides for handling of failed packet transmissions to reduce retransmission attempts and uses resynchronization to prevent tearing down of connections. Thereby, providing for more resilient connections. In an implementation, an initiator entity may determine that a negative acknowledgment indicates that an operation for a particular packet is completed in error by a target entity, and transmit to the target entity a resynchronization packet without tearing down the connection.

Reliable transport protocol and hardware architecture for datacenter networking

A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including an acknowledgment coalescing module in communication with a content addressable memory (CAM). The acknowledgment coalescing module coalesces multiple acknowledgement packets as a single acknowledgement packet to reduce the overall numbers of the packet transmission in the communication protocol system. In addition, the acknowledgment coalescing module may also provide a piggyback mechanism to carry acknowledge information in a regular data packet. Thus, the need to generate a new acknowledgement packet may be eliminated. Accordingly, the network congestion and latency may be reduced, and the communication and transmission efficiency are enhanced.

Acknowledgement coalescing module utilized in content addressable memory (CAM) based hardware architecture for data center networking

Aspects of the disclosure are directed to high performance connection cache eviction for reliable transport protocols in data center networking. Connection priorities for connection entries are determined to store the connection entries in a cache based on their connection priority. During cache eviction, the connection entries with a lowest connection priority are evicted from the cache. Cache eviction can be achieved with low latency at a high rate.

High performance cache eviction

A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.

Rate update engine for reliable transport protocol

A flow table management system can include a hardware memory module communicatively coupled to a network interface card. The hardware memory module is configured to store a flow table including a plurality of network flow entries. The network interface card further includes a flow table age cache configured to store a set of recently active network flows and a flow table management module configured to manage a duration for which respective network flow entries in the flow table stored in the hardware memory module remain in the flow table using the flow table age cache. In some implementations, age information about each respective flow in the flow table is stored in the hardware memory module in an age state table that is separate from the flow table.

Flow table aging optimized for DRAM access

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Los Gatos, CA, United States of America

Weihuang Wang