Globalfoundries Inc.

Weihua Tong

Seung Yeon Kim

Jinping Liu

Huang Liu

Haigou Huang

Hongliang Shen

Bharat V Krishnan

Changyong Xiao

Sandeep Gaan

Bongki Lee

Hsin-Neng Tai

Sang Cheol Han

Vidmantas Sargunas

Kyutae Na

Tae Hoon Kim

Ja Hyung Han

Min-Hwa Chi

Haiting Wang

Xusheng Kevin Wu

Yan Ping Shen

A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting Nin the first Ti layer vertically at a 0&#xb0; implant angle in the pFET RMG trench; annealing the Nimplanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0&#xb0;; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology

Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a 'buffer zone' or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Shallow trench isolation integration methods and devices formed thereby

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Integrated circuits having finFETs with improved doped channel regions and methods for fabricating same

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Integrated circuits having FinFETs with improved doped channel regions and methods for fabricating same

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Mechanicville, NY, United States of America

Weihua Tong