Apple Inc.

University of Southern California

Weihua Mao

Timothy R Paaske

Shu-Yi Yu

William C Athas

Nestor Tzartzanis

Lena Peterson

Timothy John Millet

Joseph P Bratt

Joshua P De Cesare

Michael J Smith

Conrad Sauerwald

David S Warren

Diarmuid P Ross

An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.

Authentication and control of encryption keys

An apparatus, a method, and a system are presented in which the apparatus may include a security circuit, a processor, and an interface controller. The security circuit may be configured to generate a keyword. The processor may be configured to determine one or more policies to be applied to usage of the keyword, and to generate a policy value. The policy value may include one or more data bits indicative of the determined one or more policies. The interface controller may be configured to generate a message including the keyword and the policy value. The interface controller may also be configured to send the message.

In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

Embedded encryption/secure memory management unit for peripheral interface controller

Disclosed herein are systems, methods, and non-transitory computer-readable storage media for generating a device dependent cryptographic key in a rate-limited way. A system configured to practice the method first receives data associated with a user. The data associated with the user can be a password, a personal identification number (PIN), or a hash of the password. Then the system performs a first encryption operation on the user data based on a device-specific value to yield first intermediate data and performs a second encryption operation on the first intermediate data based on the device-specific value to yield second intermediate data. Then the system iteratively repeats the second encryption operation until a threshold is met, wherein each second encryption operation is performed on the second intermediate data from a previous second encryption operation. The iterations produce a final cryptographic key which the system can then output or use for a cryptographic operation.

System and method for device dependent and rate limited key generation

High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer is used to drive the signal line. The receiving end of the line is connected to a jam latch, preferably followed by an n-latch, followed by the digital logic, and followed by a second n-latch. The first n-latch is eliminated in an alternate embodiment, preferably one that uses complementary data signals.

High performance clock-powered logic

High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer () is used to drive the signal line. The receiving end of the line is connected to a jam latch (), preferably followed by an n-latch (), followed by the digital logic (), and followed by a second n-latch (). The first n-latch is eliminated in an alternative embodiment, preferably one that uses complementary data signals.

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Monte Sereno, CA, United States of America

Weihua Mao