Semiconductor Manufacturing International (Shanghai) Corporation

Semiconductor Manufacturing International Corp.

Peking University

Weihai Bu

Hanming Wu

Xinpeng Wang

Wenbo Wang

Li Wang

Ru Huang

Yong Chen

Jiewen Fan

Shaofeng Yu

Yuancheng Yang

Jin Kang

Haoran Xuan

A method for forming a through-substrate-via structure includes forming a via hole in a substrate, depositing a conductive material in the via hole, forming an annular groove in the substrate surrounding the conductive material, and depositing a dielectric material in the annular groove with overhang portions of the deposited dielectric material at a top surface of the groove forming an air gap in an interior portion of the groove.

TSV interconnect structure and manufacturing method thereof

Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on the substrate and a dummy gate layer on the dummy gate dielectric layer. A dielectric layer is formed on the substrate and on sidewall surfaces of the dummy gate structure. A top surface of the dielectric layer is leveled with a top surface of the dummy gate structure. A barrier layer is formed on the dielectric layer for protecting the dielectric layer. The dummy gate layer and the dummy gate dielectric layer are removed, to form an opening in the dielectric layer without reducing a thickness of the dielectric layer. A gate dielectric layer is formed on sidewall surfaces and a bottom surface of the opening. A gate layer is formed on the gate dielectric layer to fill the opening.

Transistor and method for forming the same

A semiconductor device fabrication method is provided in which recesses are formed at source/drain positions in the substrate, removable sidewalls are formed on side walls of the recess, and the recesses then are etched to form Sigma shaped recesses. Selective epitaxial growth of substantially un-doped SiGe in the Sigma shaped recesses is performed, and the Sigma shaped recesses close to the surface of the substrate can be protected from epitaxial growth by the removable sidewalls. Epitaxial growth of SiGe doped with a P-type impurity can be performed in the Sigma shaped recesses after removing the sidewalls.

Semiconductor device and fabrication method thereof

The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections. The method of the invention is well compatible with the existing CMOS process, and it has the features of simple process and small heat budget; and in comparison with the traditional field effect transistor, by means of the quasi-SOI source/drain field effect transistor device fabricated according to the method of the invention, the leakage current can be lowered effectively, thus the power consumption of the device can be reduced.

Method for fabricating quasi-SOI source/drain field effect transistor device

Semiconductor devices and fabrication methods are provided. First metal layers are provided in a substrate including a first region and a second region. An interlayer dielectric (ILD) layer formed over the substrate includes a top surface in the second region coplanar with a bottom of a trench in the ILD layer in the first region. Through-holes are formed in the ILD layer. A polymer layer fills the through-holes and the trench in ILD layer and covers top surface of ILD layer in both regions. The polymer layer is exposed and developed to form vias, each including an upper via in the polymer layer and a lower via in ILD layer. A second metal layer is formed to fill each via on a corresponding first metal layer in both regions. The polymer layer between adjacent second metal layers is removed to form air gaps in the second region.

Semiconductor device and fabrication method

A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.

CMOS devices and fabrication method

A method is provided for fabricating an integrated semiconductor device. The method includes providing a semiconductor substrate having a first active region, a second active region and a plurality of isolation regions; forming a first gate dielectric layer on one surface of the semiconductor substrate; and forming a plurality of substituted gate electrodes, a layer of interlayer dielectric and sources/drains. The method also includes forming a first trench and a second trench; and covering the first gate dielectric layer on the bottom of the first trench. Further, the method includes removing the first dielectric layer on the bottom of the second trench; subsequently forming a second gate dielectric layer on the bottom of the second trench; and forming metal gates by filling the first trench and second trench using a high-K dielectric layer, followed by completely filling the first trench and the second trench using a gate metal layer.

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Shanghai, China

Weihai Bu