Mstar Semiconductor, Inc.

Weigang Sun

Chao-Tung Yang

Hung Chuan Pai

Various embodiments of a flip-flop and a frequency dividing circuit are provided. In one aspect, a flip-flop includes an input stage and a latch stage. The input stage is capable of converting an input signal to an output signal under the control of a first clock signal and a second clock signal. The latch stage is capable of latching the output signal under the control of a third clock signal and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have different phases.

Flip-flop and frequency dividing circuit with flip-flop

The invention discloses an interference cancellation circuit for a receiver to process an input signal which is carried on a first carrier frequency and includes a transmitted signal and at least one interference signals. The interference cancellation circuit comprises a down-converter for converting the input signal to dc location to generate a down-converted signal; a first path circuit for processing the down-converted signal to generate a first processed signal which includes the transmitted signal and the interference signals; a second path circuit for processing the down-converted signal to generate a second processed signal which includes only the interference signals; and a combiner for generating an output signal by combining the first processed signal and the second processed signal.

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La Palma, CA, United States of America

Weigang Sun