Texas Instruments Corporation

Reed Semiconductor Corp.

Weidong Zhu

Wenkai Wu

Hal Chen

Xuening Li

Shishuo Zhao

Kuang-Yao Cheng

Jialun Du

Wnenkai Wu

Qian Chen

Cheng-Wei Chen

An apparatus includes a plurality of switches connected in parallel between an input terminal and an output terminal of a power bus, a plurality of current sensing circuits coupled to the plurality of switches, wherein each current sensing circuit is coupled to a corresponding switch, and a plurality of current sharing circuits configured to receive current sensing signals from the plurality of current sensing circuits and generate a plurality of gate drive signals to control the plurality of switches so as to achieve a predetermined current distribution among the plurality of switches.

Current sharing apparatus and control method

A buck converter with an asymmetric threshold voltage of its gate drive circuit design for improving power efficiency while keeping the gate drive design simple.

Buck converter system with an asymmetric threshold voltage gate drive circuit design

A multiphase buck converter that includes smart two-phase power stages for reducing switching losses. Each of the smart power stages includes a first high side switch, a second high side switch, a first low side switch, a second low side switch, a switching capacitor, a first inductor, and a second inductor. The exemplary multiphase buck converter includes two such smart power stages and a multiphase controller for generating PWM signals for driving the two smart power stages synchronously.

Two-phase smart power stage (SPS) for multiphase buck converters

Methods, apparatus, systems, and articles of manufacture are disclosed for regulated hybrid converters. An example apparatus includes an input terminal; an output terminal, a first converter circuit coupled between the input terminal and an intermediate node, the first converter circuit having a first switch node, a second converter circuit coupled between the intermediate node and the output terminal, the second converter circuit having a second switch node; a first inductor coupled between the first switch node and the second switch node, and a second inductor coupled between the second switch node and the output terminal.

Methods and apparatus for regulated hybrid converters

An apparatus includes first and second power converter stages, each stage having a primary side and a secondary side. The primary side of the first stage includes a switch Tcoupled to a voltage source and a switch Tcoupled to the switch T. The primary side of the second stage includes a switch Tcoupled to the switch Tand a switch Tcoupled to the switch Tand to the voltage source. The apparatus includes a control circuit to control an on/off time of the switches. The control circuit includes four gate driver controllers to control the on/off time of the switches and a current sharing control section to increase or decrease the on time of a switch based on a comparison of a current through one of multiple output inductors to an average current through the multiple output inductors.

Serial input power converter

One embodiment includes a power regulator system. The system includes a switch control stage configured to generate at least one activation signal based on a pulse-width modulation (PWM) signal and to control a respective at least one switch to generate an output voltage. The system also includes a feedback stage configured to generate the PWM signal based on a ramp signal and a feedback voltage that is based on the output voltage. The system further includes a ramp generator stage configured to adaptively generate the ramp signal based on the output voltage and based on the at least one activation signal.

Power regulator system with adaptive ramp signal generator

Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.

Systems and methods of smooth light load operation in a DC/DC converter

Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current.

Growing community of inventors

East Lyme, CT, United States of America

Weidong Zhu