Texas Instruments Corporation

Weidong Tian

Jeffrey Alan West

Byron Lovell Williams

Allan T Mitchell

Rajni J Aggarwal

Bradley David Sucher

David Leonard Larkin

Zafar Imam

Pinghai Hao

Imran Khan

Jozef C Mitros

Tathagata Chatterjee

YuGuo Wang

Victor Ivanov

Ning Tan

Shanjen “Robert” Pan

Binghua Hu

Louis N Hutter

James Robert Todd

Ming-Yeh Chuang

Eric W Beach

Shanjen Pan

Pushpa Mahalingam

Sopa Chevacharoenkul

Xinfen Chen

William E Nehrer

Marshall O Cathey, Jr

David C Guiling

Eric William Beach

A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.

Structure and method for improving high voltage breakdown reliability of a microelectronic device

A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.

An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.

Low cost flash memory fabrication flow based on metal gate process

A method and structure for improving high voltage breakdown reliability of a microelectronic device, e.g., a galvanic digital isolator, involves providing an abatement structure around metal plate corners of a high voltage isolation capacitor to ameliorate the effects of an electric field formed thereat during operation of the device due to dielectric discontinuity.

An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

Method of improving bipolar device signal to noise performance by reducing the effect of oxide interface trapping centers

Fabrication flow based on metal gate process for making low cost flash memory

A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (I) results from the fluorine implant.

On current in one-time-programmable memory cells

Current in one-time-programmable memory cells

A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.

Fluorine implant under isolation dielectric structures to improve bipolar transistor performance and matching

In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

Electrically erasable programmable non-volatile memory

A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7&#xd7;10atoms/cmand 2.3&#xd7;10atoms/cm. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7&#xd7;10atoms/cmand 2.3&#xd7;10atoms/cm. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7&#xd7;10atoms/cmand 2.3&#xd7;10atoms/cm.

Zero temperature coefficient capacitor

A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is &#x3c;1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes &#x2266;100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.

Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes

The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (), obviating overstress or break down damage to a focal device structure () that might result from uncontrolled dissipation of the aberrant charge. A substrate () has first and second intermediate structures () disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure () is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure () is disposed contiguously atop the first conductive structure and the first intermediate layer. A void () is formed in a peripheral region () of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure () is disposed atop the third intermediate structure such that it couples the substrate through the void.

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Dallas, TX, United States of America

Weidong Tian