Broadcom Corporation

Cisco Technology, Inc.

Avago Technologies General IP Pte, Ltd.

Weidong Rick Li

Nelson Ray Sollenberger

Ruei-Shiang Suen

Edward Wayne Boyd

Jaroslaw Wojtowicz

Ahmadreza Rofougaran

Maryam Rofougaran

Hooman Darabi

Vafa James Rakshani

Claude G Hayek

Frederic Christian Marc Hayem

Sanjeev Ukhalkar

One embodiment provides a system for performance monitoring in a passive optic network (PON). The system includes an optical line terminal (OLT) and an optical network unit (ONU). The OLT includes an optical transceiver configured to transmit optical signals to and receive optical signals from the ONU, and a performance monitoring mechanism configured to monitor performance of the PON based on received optical signals.

Performance monitoring in passive optical networks

One embodiment provides an EPON for transporting RF signals. The system includes a reference clock, an ONU, and an OLT. The ONU includes a mechanism for receiving a frequency and phase-reference signal from the OLT, a mechanism for receiving an RF signal, an ADC for converting the RF signal into a digital signal using a sampling signal associated with the frequency and phase-reference signal, a mechanism for assembling at least a portion of the digital signal into a packet, a mechanism configured to timestamp the packet, and an optical transceiver. The OLT includes a mechanism for receiving the packet, a buffer, a delay mechanism configured to delay reading the received packet from the buffer for a predetermined amount of time, and a DAC for converting the digital signal included in the packet back to RF domain using a clock signal associated with the frequency and phase-reference signal.

RF signal transport over passive optical networks

Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching from a core processor to a DSP. At least a first bus that couples the core processor to a message processor and at least a first clock signal that clocks the core processor may be switched. At least a second bus that couples the DSP to the message processor and at least a second clock signal that clocks the DSP may be switched. When a loss of clock signal from the core processor or the DSP to the message processor is detected, a third clock signal for clocking the message processor may be generated. The message processor switch significantly reduces the amount of bandwidth utilized for transfer of data between the core processor and the DSP and provides incremental redundancy (IR) without high hardware cost and software MIPS, thereby providing significant improvement in system performance.

Method and system for a message processor switch for performing incremental redundancy in edge compliant terminals

A voice data and RF integrated circuit (IC) includes an RF transceiver module that produces received data based on a received RF signal and that produces a transmitted RF signal based on transmit data. A memory module includes a first read only memory (ROM) segment for storing a first plurality of operational instructions, and a first random access memory (RAM) segment for storing a second plurality of operational instructions. A first processing module executes the plurality of operational instructions that include baseband processing to generate input data from the received data, and to produce the transmit data from input data. A first memory interface provides direct downloading of the second plurality of operational instructions from the external memory to the first RAM segment.

Direct memory download in a voice data and RF integrated circuit and method for use therewith

An integrated circuit radio receiver includes radio frequency ('RF') front-end circuitry to receive a wireless signal and to produce digital data. The integrated circuit radio receiver includes a baseband processor is operable to process the digital data, in which the baseband processor is operable to produce a format designation based on the digital data. The baseband processor includes a plurality of digital filtering logic in which each of the digital filtering logic includes a level of digital filtering. The baseband processor further includes logic operable to select between each digital filtering logic of the plurality of digital filtering logic based upon the format designation, and to process the digital data with the selected level of digital filtering.

Processing received digital data signals based on a received digital data format

Methods and systems for performing interleaved to planar transformation operations in a mobile terminal having a video display are disclosed. Aspects of one method may include extracting similar color space components from a received block of interleaved YUV color space format video data as data is received, where the block may comprise 128 bits. The similar color space components may be extracted and transferred to a memory, where each type of the similar color space components may be stored contiguously in separate portions of the memory in planar format. The transferring of data may be via direct memory access of 32-bit words. When the line buffer that is receiving the interleaved video data is full, a direct memory access operation may be initiated. Direct memory access operation may also be initiated when the data for a similar color space component for a complete horizontal line is extracted.

Method and system for performing interleaved to planar transformation operations in a mobile terminal having a video display

Certain aspects of a digital baseband transmitter with digital RF/IF support in GSM/GPRS/EDGE compliant devices may comprise receiving digitized data within a chip. A control signal may be generated within the chip indicating whether the received digitized data is to be processed by an IF processing interface or a digital RF processing interface. The baseband processor has the capability to work together with different kinds of RF chips on the market and since this design is implemented on a single module, most of the circuits are shared which reduces the die size significantly. This design also provides a customer more flexibility to choose among different RF vendors.

Digital baseband transmitter with digital RF/IF support in GSM/GPRS/EDGE compliant handsets

A method and system for digital baseband receiver with digital RF/IF/VLIF support in GSM/GPRS/EDGE compliant handsets. The method may comprise receiving an input signal which may be a digital RF signal, IF or VLIF signals, and the input signal may comprise of I and Q components. The serial digital RF signal may be converted to a parallel digital formatted signal, the latter of which may be transferred to an input of a multiplexer. The received IF signal or VLIF signal may be filtered and transferred to the input of the DU which may convert the VLIF signal to a baseband signal by processing the VLIF signal with a CORDIC algorithm. The DU may bypass processing the IF signal. The output of the DU may be transferred to the input of the multiplexer, such that the multiplexer may select the parallel digital formatted signal or the output of the DU.

Method and system for digital baseband receiver with digital RF/IF/VLIF support in GSM/GPRS/EDGE compliant handsets

An integrated circuit radio receiver includes radio frequency ('RF') front end circuitry for receiving and transmitting digital data received through a wireless interface. A baseband processor is operable to process the digital data received through the wireless interface. A plurality of digital filtering logic is included wherein each digital filtering logic includes a level of digital filtering based upon a received digital data signal format. The integrated circuit radio receiver includes logic that is operable to select between each digital filtering logic of the plurality of digital filtering logic based upon the received digital data signal format to process the digital data received through the wireless interface with the selected level of digital filtering.

Certain aspects of reducing power consumption in communication devices may comprise deasserting a signal indicating that an on-chip UART may be ready to receive data. The deasserted signal may be asserted when the on-chip UART is not ready to receive data. The deasserted signal and asserted signal may be a RTS signal or a CTS signal. The signal may be deasserted when an on-chip processor wakes up from a low power state. The deasserted signal may be asserted when an on-chip processor enters a low power state. The on-chip UART may be adapted to receive and process data from an off-chip processor when the signal is deasserted. The data may be queued externally to the on-chip UART by an off-chip processor when the deasserted signal is asserted. The on-chip UART may be adapted to receive an interrupt signal that causes it to wake up from a low power state.

Method and system for reducing power consumption of handsets through UART auto flow control

Methods and systems for video format transformation in a mobile terminal having a video display may include converting interleaved YUV 4:2:2 color space video data to YUV 4:2:0 color space video data as the interleaved YUV 4:2:2 color space video data is received. The conversion may use Y, U, and V components in the interleaved YUV 4:2:2 color space video data for a horizontal line of video data. The conversion may also use only a Y component in the interleaved YUV 4:2:2 color space video data for a previous horizontal line or a successive horizontal line of video data. The converted 4:2:0 color space video data may be transferred to memory via, for example, direct memory access. The YUV 4:2:0 color space video data may be transferred to the memory as, for example, 32-bit words.

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Saratoga, CA, United States of America

Weidong Rick Li