Advanced Micro Devices Corporation

Spansion Llc.

Globalfoundries Inc.

Weidong Qian

Mark T Ramsbey

Tazrien Kamal

Jean Y Yang

Kouros Ghandehari

Minh Van Ngo

Sameer S Haddad

Yu Nan Sun

Hiroyuki Kinoshita

Jean Yee-Mei Yang

Hirokazu Tokuno

Jeff P Erhardt

Taraneh Jamali-Beh

Angela Tai Hui

Scott Allan Bell

Mark W Randolph

Cyrus E Tabery

Eric N Paton

Hidehiko Shiraiwa

Mark S Chang

Simon S Chan

Joong Jeon

Alexander H Nickel

Hieu T Pham

Jaeyong Park

Inkuk Kang

Allison Holbrook

Cinti Xiaohua Chen

Christopher H Raeder

David H Matsumoto

Phillip Lawrence Jones

Nga-Ching Wong

Ashok M Khathuria

Christopher Foster

Kelwin King Wai Ko

A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.

Method for forming bit lines for semiconductor devices

A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (SiN) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or SiNand forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or SiNas a mask when etching a pattern in the layer of semiconducting material.

Triple layer anti-reflective hard mask

A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.

A structure for electrically isolating semiconductor devices includes a semiconducting layer and a layer of aluminum oxide formed in a pattern over the semiconducting layer, where the pattern exposes a portion of the semiconducting layer. The structure further includes an electrical isolation region formed in the exposed portion of the semiconducting layer, where the isolation region does not substantially encroach a region beneath the layer of aluminum oxide.

Isolation region bird's beak suppression

A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.

Bit line implant

A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.

Void free interlayer dielectric

A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.

Interface layer between dual polycrystalline silicon layers

Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer. A multi-bit flash memory array is also disclosed, comprising a bitline region in a substrate, a first dielectric layer overlying the substrate substantially adjacent to and substantially exposing the bitline region, a charge trapping layer overlying the first dielectric layer substantially adjacent to and substantially exposing the bitline region, a bitline oxide isolation structure or layer extending continuously over the bitline region and charge trapping layer, the isolation structure comprising a single dielectric material layer formed by the radical oxidation process, and a conductive wordline overlying the bitline oxide isolation structure or layer.

Radical oxidation for bitline oxide of SONOS

The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or 'packed' within the same or a smaller area.

LDC implant for mirrorbit to improve Vt roll-off and form sharper junction

A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.

Memory device and method of simultaneous fabrication of core and periphery of same

The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.

Disposable hard mask for memory bitline scaling

The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be 'packed' within the same or a smaller area.

Bitline implant utilizing dual poly

A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

Hard mask spacer for sublithographic bitline

A technique for forming at least part of an array of a dual bit memory core is disclosed. A Safier material is utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

Narrow bitline using Safier for mirrorbit

A core memory array having a plurality of charge trapping dielectric memory devices. The core memory array can include a substrate having a first semiconductor bit line and a second semiconductor bit line formed therein and a body region interposed between the first and the second bit lines. Over the body region can be formed a first dielectric layer disposed, a dielectric charge trapping layer and a second dielectric layer. At least one word line can be disposed over the second dielectric layer, which defines a channel within the body region. Each bit line can include a bit line contact assembly having a locally metalized portion of the bit line and a conductive via traversing a dielectric region.

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Sunnyvale, CA, United States of America

Weidong Qian