Texas Instruments Corporation

Amlogic Co., Limited

Weicheng Zhang

Jian Liang

Shu-Sun Yu

Ming Shi

Yanli Fan

Huanzhang Huang

Chieh-Yuan Chao

Wei-Hua Zou

Roland Sperlich

Linghan Xie

Wei Zhao

Mark William Morgan

Chen Feng

Jianzhang Xie

Ming Luo

Yangwei Yu

In described examples, a boost converter includes an inductor, a voltage input, a current regulator, an intermediate node, a transistor, and a regulation circuit. The inductor has first and second terminals. The voltage input provides an input voltage, and is coupled to the first inductor terminal. The current regulator has current regulator input and output. The current regulator input is coupled to the second inductor terminal. The current regulator allows current to flow from the current regulator input to the current regulator output, and not vice versa. The intermediate node provides a node voltage. The transistor includes a source, a drain, and a gate. The drain is coupled to the current regulator output via the intermediate node. The regulation circuit includes a first regulation input coupled to receive the input voltage, a second regulation input coupled to the intermediate node, and a regulation output coupled to the gate.

Output regulated boost converter

A DC-DC converter control circuit includes an error amplifier, a voltage-to-current conversion circuit, an oscillator circuit, and a pulse frequency modulation (PFM) control circuit. The error amplifier is configured to generate a difference voltage as a difference of an output voltage of the DC-DC converter circuit and a reference voltage. The voltage-to-current conversion circuit configured to convert the difference voltage to a difference current. The oscillator circuit is configured to generate a clock signal at a predetermined frequency for pulse width modulation. The PFM control circuit is configured to disable the oscillator circuit, based on the difference current, for PFM operation.

DC-DC converter with pulse modulation control circuit

A voltage converter includes an inductor, a transistor, a comparator, an error amplifier, and a slope generator circuit. The transistor has a control input and first and second transistor current terminals. The first current terminal is coupled to the inductor. The comparator has first and second comparator inputs and a comparator output. The comparator output is usable to control the transistor's control input. The error amplifier has an error amplifier input and an error amplifier output. The error amplifier output is coupled to the first comparator input. The slope generator circuit is coupled to at least one of the first or second comparator inputs. The slope generator circuit is configured to generate a slope compensation current which, during at least a portion of each cycle of operation of the voltage regulator, varies approximately exponentially with respect to time.

Exponential-based slope compensation

A converter system includes a first switch, a first sensing unit configured to generate a first sensed signal proportional to a current through the first switch, a second sensing unit () configured to generate a second sensed signal based on a difference between a reference voltage and a feedback voltage, a DC compensation unit configured to generate a slope peak DC signal relative to a slope peak of a slope compensation signal, and a signal combination unit configured to generate a control signal based on the first and second sensed signals, the slope compensation signal and the slope peak DC signal to switch off the first switch.

DC-DC converter with current loop gain

A DC-DC converter controller includes a transistor driver, a flip-flop, a comparator, an integrator circuit, a switch, and a pulse generator circuit. The flip-flop includes an output coupled to an input of the transistor driver. The comparator includes an output coupled an input of the flip-flop. The integrator circuit includes an output coupled to an input of the comparator. The switch includes a first terminal coupled to the output of the integrator circuit, and a second terminal coupled to ground. The pulse generator circuit includes an input coupled to an output of the transistor driver, and an output coupled to a third terminal of the switch.

Boost converter

A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Differential driver with pull up and pull down boosters

A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

Differential receiver

Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.

Method and apparatus for Vernier ring time to digital converter with self-delay ratio calibration

An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.

Digital phase locked loop

A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.

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Shanghai, China

Weicheng Zhang