Texas Instruments Corporation

Apple Inc.

Weibiao Zhang

J Randall Cooper

Bruno Werner Garlepp

Jafar Savoj

Richard K Hester

Patrick Peter Siniscalchi

Bertan Bakkaloglu

Kyl Wayne Scott

John Eric Kunz, Jr

Donald Cook Richardson

Daniel J Fritchman

Dening Wang

Gin S Yee

Ke Yun

Liang Wang

Craig P Finlinson

Venkatesh B Acharya

Tao Zeng

Various techniques for implementing resistive temperature sensors that rely on the resistors' temperature sensitivity to provide temperature sensing are disclosed. Temperature sensitive resistors may be implemented in a resistor stack in combination with a resistor stack of resistors that are relatively temperature indifferent. Various temperature sensor circuits implementing these temperature sensitive resistors are also disclosed. A temperature sensor circuit may implement the temperature sensitive resistors along with the resistors that are relatively stable with temperature to output a voltage signal that is indicative of the temperature sensed by the circuit. In some instances, the signal from the temperature sensitive resistors is increased through the use of a feedback resistor loop.

Resistive hotspot temperature sensor

An apparatus includes an integrated circuit that includes an in-circuit power switch coupled to a power supply node, a functional circuit coupled between the in-circuit power switch and a ground node, a test circuit, and a test power switch coupled to the test circuit, wherein the test power switch is a replica of the in-circuit power switch. The test circuit is configured to determine characteristics of the test power switch, and to measure a voltage difference across the in-circuit power switch. The test circuit is also configured to use the characteristics of the test power switch and the voltage difference to determine a power consumption of the functional circuit.

Non-invasive on-chip power measurement technique

A system and method for efficiently receiving analog input signals. In various embodiments, a functional unit includes a switch in its interface logic. The switch receives an analog input signal, and when enabled, conveys the received input signal as an analog output signal. The switch is enabled when the received enable signal is asserted. However, when the power supply voltage is at a logic low level, an output n-type device is disabled while an output p-type device is enabled. A guard p-type device serially connected with the output p-type device is disabled by other devices used to control the guard p-type device. The control devices also ensure that the body terminals of the guard p-type device and other p-type devices receive a logic high level regardless of the power supply value, which prevents forward bias currents in parasitic diodes of the p-type devices.

Analog switches immune to power sequence

A highly granular voltage regulator is disclosed. The voltage regulator circuit includes first and second current mirror circuits coupled to first and second control circuits, respectively. The voltage regulator circuit further includes an amplifier having an inverting input and a non-inverting input. The first current mirror circuit is coupled to the non-inverting input, whereas the second current mirror circuit is coupled to the inverting input. The first control circuit is operable to control a current provided by the first current mirror circuit, while the second control circuit is operable to control a current provided by the second current mirror circuit.

Highly granular voltage regulator

An apparatus comprises a first PFET including a first intrinsic body diode; an electrostatic discharge (ESD) subcircuit coupled to a source of the first PFET; a reverse bias voltage element, such as a zener diode, an anode of which is coupled to a gate of the first PFET; a second PFET having a source coupled to a cathode of the zener diode a capacitor coupled to a gate the second PFET; and a first resistor coupled to the gate of the second PFET. The apparatus can protect against both positive and negative electro static transient discharge events.

Low-impedance high-swing power supply with integrated high positive and negative DC voltage protection and electro-static discharge (ESD) protection

A battery cell tab monitoring apparatus includes a conductive element electrically connected between two battery cells. The conductive element is connected to a sensing circuit including a pull-down current source connected to pull current from the conductive element and/or a pull-up current source connected to drive current into the conductive element. A voltage measuring circuit is connected to sense voltages during operation of the pull-down current source and the pull-up current source to be used to determine the status of the conductive element. For instance, voltages beyond certain fixed or variable thresholds indicate that the conductive element is flexing or cracking, which can be a precursor to its breaking. Voltages beyond other fixed or variable thresholds indicate that the conductive element is fully disconnected. The current sources used to push and pull the sensing currents may be used to bring the battery cells into balance when an imbalance is detected.

Battery cell tab monitor

A control circuit of a battery power-path management circuit establishes a first power path between a battery input node and an output node when the input node voltage is larger than a charger input node voltage and a second power path between the charger input node and the output node when the voltage on the charger input node is larger than the battery input node voltage. It controls the second power path to provide power to the output node, enabling battery charging and protection over a battery voltage range from about zero volts. It has low power consumption and can support wide-swing power supply voltage from as low as one volt to as high as maximum allowed Vds of drain-extended devices. It can use smaller device sizes because the PMOS switch gate voltage is 0V when the power supply is not too high.

Low-voltage dual-power-path management architecture for rechargeable battery monitoring solutions

A voltage protection circuit that has a protection transistor coupled between a voltage supply pin of an integrated circuit and a voltage output terminal of the integrated circuit. A biasing circuit is coupled to a control node of the protection transistor and configured to cause the protection transistor to turn on to form a low impedance path between the voltage supply pin and the voltage output terminal when a positive supply voltage is coupled to the voltage supply terminal and to cause the protection transistor to turn off when a negative supply voltage is coupled to the voltage supply terminal. An electro-static discharge (ESD) protection circuit may also be connected between the voltage supply pin and a reference node that is configured to conduct a negative static discharge current for period of time, and to not conduct a negative current continuously.

Reverse voltage protection circuit

A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (and) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion. Furthermore, the distortion as a result of the clock signal fed through each transistor in the first and second subcircuit portions cancel each other.

Current-steering digital-to-analog converter having a minimum charge injection latch

A gain controlled voltage controlled oscillator. A current controlled oscillator is adapted to provide an output signal oscillating at a frequency controllable by controlling a current applied thereto. A first current source provides a first control current controllable by controlling a voltage applied thereto that has a predetermined range. A first current mirror is adapted to mirror the control current to the current controlled oscillator. A second current source is adapted to provide a second control current for mirroring to the current controlled oscillator by the first current mirror when the control voltage is in a low portion of the range.

Gain control circuits for voltage controlled oscillators

A dithering method is provided for sigma-delta converters in a deep-submicron process. The dither is a random interleaving of quantizer thresholds levels. The random interleaving dither is more effective than previous static dither methods to remove idle channel tones of sigma-delta analog-to-digital converters (ADC). The dither is easy to implement and takes less area than other dynamic dither methods.

Random interleaving dither for sigma-delta analog-to-digital converters

A Sigma-Delta Analog-to-Digital Converter (ADC) having efficient dithering that removes the idle channel tones of the sigma-delta converter is disclosed herein. These idle channel tones are reduced or removed by stretching the threshold window of the multi-level quantizer. A dithering sequence is added by stretching the thresholds window randomly. The randomly stretched window destructs the periodicity of sigma-delta ADC modulator's output sequence and, thus, removes the idle channel tones. Compared with conventional methods, the Sigma-Delta ADC in accordance with the present invention has less SNR penalty and is simple to implement. Moreover, the sigma-delta ADC in accordance with the present invention has a higher allowed input dynamic range and higher signal-to-noise-plus-distortion-ratio (SNDR) than conventional modulator dithering schemes.

Dithering method for sigma-delta analog-to-digital converters

A method of configuring a switch-network to implement programmable gain devices such as Programmable Gain Amplifiers (PGAs). The method provides high-accuracy and low-distortion with small area requirements and less sensitivity to process and temperature variations when compared with traditional programmable gain architectures where the gain is determined by a ratio between one or more fixed resistors and one or more programmable resistors.

Method of configuring a switch network for programmable gain amplifiers

A pipelined analog-to-digital converter includes a first stage 700 of an analog-to-digital converter having a first resolution. The first stage 700 includes a three capacitor switched capacitor circuit. The analog-to-digital converter further includes one or more subsequent analog-to-digital converter stages 200. The first and subsequent stages 700 and 200 are pipelined together to provide a digital output signal.

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Plano, TX, United States of America

Weibiao Zhang