Sigmastar Technology Ltd.

Wei Zhu

Bo Lin

Chao Li

Chengwei Zheng

Donghao Liu

Fabo Bao

A convolution calculation apparatus applied for convolution calculation of a convolution layer includes a decompression circuit, a data combination circuit and a calculation circuit. The decompression circuit decompresses compressed weighting data of a convolution kernel of the convolution layer to generate decompressed weighting data. The data combination circuit combines the decompressed weighting data and non-compressed data of the convolution kernel to restore a data order of weighting data of the convolution kernel. The calculation circuit performs calculation according to the weighting data of the convolution kernel and input data of the convolution layer. Since the compressed weighting data of the convolution kernel is transmitted to the convolution calculation apparatus in advance, the compressed weighting data is first decompressed and then convolution calculation is performed accordingly, hence reducing the storage amount and transmission bandwidth used by the convolution kernel in an electronic apparatus.

Convolution calculation apparatus and method

A virtual memory management method applied to an intelligent processor including an operation accelerator includes: determining m storage units from a physical memory, the m storage units forming a virtual memory; dividing the m storage units into n storage groups; determining an address mapping relationship for each storage group to obtain n address mapping relationships, the n address mapping relationship being correspondence of between n virtual addresses of the virtual memory and physical addresses of the m storage units, where m and n are dynamically updated according to requirements of the operation accelerator. In the method, the number of the storage units in each storage group can be configured according to requirements of the operation accelerator, and a data storage bit width and a data storage depth of the virtual memory are dynamically updated to thereby improve data access efficiency.

Virtual memory management method and processor

A data temporary storage apparatus includes a moving unit coupled to a first storage unit and multiple second storage units. The moving unit receives a moving instruction having contents including a read address, a destination address and a predetermined moving rule. The moving unit further executes the moving instruction to fetch input data by row from the first storage unit according to the read address, and to temporarily stores one after another in an alternate and sequential manner the data in each row to each of the second storage units indicated by the destination address. The data moving, data reading and convolution approaches of the present invention implement in parallel data moving and a convolution operation, achieving a ping-pong operation of convolution units and enhancing convolution efficiency, while reducing memory costs since configuring two data storage spaces in a memory is not necessary.

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Xiamen, China

Wei Zhu