Micron Technology Incorporated

Wei Zhou

Bret K Street

Kyle K Kirby

Kunal R Parekh

Thiagarajan Raman

Mark E Tuttle

Eiichi Nakano

Benjamin L McClain

Aibin Yu

Chien Wen Huang

Zhaohui Ma

Ying Ta Chiu

A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material sintering therein.

Monolithic conductive column in a semiconductor device and associated methods

A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

Monolithic conductive cylinder in a semiconductor device and associated methods

A semiconductor device assembly including a first semiconductor device having a front side and a back side opposite of the front side, metal interconnects formed on the back side, and a polymer material deposited over the first semiconductor device to encapsulate the sidewalls, back side, and metal interconnects. The first semiconductor device is planarized to expose the upper surface of the metal interconnects. The assembly further includes a second semiconductor device having a top side and a bottom side opposite of the top side, a polymer material deposited over the second semiconductor device to encapsulate the sidewalls and bottom side. The second semiconductor device is stacked over the first device and hybrid bonded together such that each metal interconnect on the first semiconductor device back side aligns with and electrically couples to a corresponding metal interconnect on the second semiconductor device bottom side.

Polymer coated semiconductor devices and hybrid bonding to form semiconductor assemblies

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

Solder based hybrid bonding for fine pitch and thin BLT interconnection

Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.

Conductive buffer layers for semiconductor die assemblies and associated systems and methods

Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

Apparatus including integrated pads and methods of manufacturing the same

A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

Grindable heat sink for multiple die packaging

A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.

Monolithic conductive columns in a semiconductor device and associated methods

A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

Bond pad with micro-protrusions for direct metallic bonding

A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

Methods and systems for manufacturing semiconductor devices

A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

Semiconductor devices including one or more interfacing segments patterned within an outer protective layer and associated systems and methods are disclosed herein. The one or more interfacing segments may provide attachment interfaces/surfaces for connection pads. The one or more interfacing segments or a portion thereof may remain uncovered or exposed and provide warpage control for the corresponding semiconductor device.

Growing community of inventors

Boise, ID, United States of America

Wei Zhou