Nan Ya Technology Corporation

Wei-Zhong Li

Hsih-Yang Chiu

Chien-Chung Wang

Yi-Ting Shih

Ting-Cih Kang

A semiconductor wafer includes a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction.

Semiconductor wafer and testing module

A semiconductor device is provided. The semiconductor device includes a substrate having an active area and a fuse component. The fuse component has a bottom electrode in the active area, a first dielectric layer on the active area and a top electrode on the first dielectric layer. The semiconductor device also includes a second dielectric layer on the active area and surrounding the first dielectric layer.

Semiconductor device having fuse component

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

Semiconductor structure having fuse below gate structure and method of manufacturing thereof

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Semiconductor device with programmable structure and method for fabricating the same

The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.

Memory device having merged active area

A multi-stacking carrier structure includes an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer.

Multi-stacking carrier structure and method for fabricating the same

The present application discloses a semiconductor device, including a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure positioned on the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an inter-dielectric layer on a substrate; a conductive pad in the inter-dielectric layer; and a multi-stacking carrier structure including a first tier on the inter-dielectric layer, a second tier on the first tier, and a third tier on the second tier.

Semiconductor device with multi-stacking carrier structure

A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

Method for preparing semiconductor device with wire bond

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

Semiconductor device with leakage current guide path and method for fabricating the same

A semiconductor structure includes a substrate, first and second transistors, first and second fuses, a contact structure, and a dielectric layer. The substrate has first and second device regions, and a fuse region. The first and second transistors are respectively above the first and second device regions. The first fuse is electrically connected to the first transistor and includes a first fuse active region having first and second portions. The second fuse is electrically connected to the second transistor and includes a second fuse active region having third and fourth portions. The contact structure interconnects the second portion and the third portion, wherein the first portion and the fourth portion are on opposite sides of the contact structure. The dielectric layer is between the contact structure and the fuse region of the substrate.

Semiconductor structure

The present application provides an anti-fuse one-time programmable (OTP) memory array and a manufacturing method of the anti-fuse one-time programmable (OTP) memory array. The memory array includes: active areas; pairs of programming word lines and read word lines; and dummy word lines. The active areas extend along a first direction in a semiconductor substrate, and are separately arranged along a second direction. The programming word lines, the read word lines and the dummy word lines extend along the second direction over the semiconductor substrate. A region in which a pair of programming word line and read word line are intersected with one of the active areas defines a unit cell in the memory array. The dummy word lines respectively lie between adjacent pairs of programming word lines and read word lines. A region in which one of the dummy word lines is intersected with one of the active areas defines an isolation transistor.

One-time programmable memory array and manufacturing method thereof

The present application discloses a method for characterizing a resistance state of a programmable element of an integrated circuit. The method includes the steps of setting a first programming voltage of a first polarity to program the programmable element of the integrated circuit, setting a first read voltage of the first polarity to the integrated circuit at a first temperature to obtain a first read current, and a first resistance is derived from the first read current, setting the first read voltage of the first polarity to the integrated circuit at a second temperature to obtain a second read current, the second temperature is at least 50&#xb0; C. higher than the first temperature, and a second resistance is derived from the second read current, and comparing the first resistance and the second resistance to characterize the resistance state of the programmable element.

Growing community of inventors

Taoyuan, Taiwan

Wei-Zhong Li