Spansion Llc.

Advanced Micro Devices Corporation

Cypress Semiconductor Corporation

Other

Globalfoundries Inc.

Fasl LLC

Wei Zheng

Mark W Randolph

Kuo-Tung Chang

Chi K Chang

Zhizheng Liu

Hiroyuki Kinoshita

Yi He

Mark T Ramsbey

Meng Ding

Hidehiko Shiraiwa

Nicholas H Tripsas

Unsoon Kim

Ashot Melik-Martirosian

Timothy J Thurgate

Tazrien Kamal

Chungho Lee

Sung-Yong Chung

Jack F Thomas

Zoran Krivokapic

Arvind Halliyal

Darlene G Hamilton

Chih-Yuh Yang

Gulzar Ahmed Kathawala

Effiong Etukudo Ibok

Ning Cheng

Jean Y Yang

Joong Jeon

Ming Sang Kwan

Harpreet Kaur Sachar

Michael A VanBuskirk

David Michael Rogers

Minghao Shen

Fred Cheung

Sheung-Hee Park

Fred T K Cheung

Mimi Xuefeng Qian

Gabrielle Wing Han Leung

Kwadwo A Appiah

Angela Tai Hui

Richard M Fastow

Binh Quang Le

Yue-Song He

Takashi Whitney Orimoto

Robert B Ogle

Lei Xue

An Chen

Satoshi Torii

Edward Hsia

Edward Franklin Runnion

Kulachet Tanpairoj

Sung-Chul Lee

Yun Wu

Xin M Zhao

Ihsan Djomehri

Ken Tanpairoj

Ning Cheung

Sugimo Rinji

This disclosure is about invention of fuel cells comprising vertically free-standing graphene-containing carbon nanosheets in the components, and methods of making thereof. Performance enhancement effect of the fuel cell is achieved by using vertically free-standing graphene-containing carbon nanosheets as: 1) surface coating of electrically conducting components, 2) and/or a geometric geometric structural supporter of additive catalyst materials, 3) and/or a synergic catalytic nano-composite

Fuel cells using vertically free standing graphene and carbon nanosheets

An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

Flash memory cells having trenched storage elements

A semiconductor device () for improved charge dissipation protection includes a substrate (), a layer of semiconductive or conductive material (), one or more thin film devices () and a charge passage device (). The thin film devices () are connected to the semiconductive or conductive layer () and the charge passage device () is coupled to the thin film devices () and to the substrate () and provides a connection from the thin film devices () to the substrate () to dissipate charge from the semiconductive/conductive layer () to the substrate ().

Method and apparatus for protection against process-induced charging

Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.

Method for fabricating memory cells having split charge storage nodes

A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.

Memory system with Fin FET technology

In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO.

Memory devices containing a high-K dielectric layer

A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Strapping contact for charge protection

A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase pulse count corresponding to a preliminary erase operation during which a relatively small portion of a sector is erased. The adjustment of the erase bias voltage in this manner enables the rest of the sector to be erased using erase bias voltages that are better suited to the current erase characteristics of the sector.

Erasing flash memory using adaptive drain and/or gate bias

A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory

A dual-bit memory device is provided which includes trench isolation material disposed near bit line contact areas. For example, in one implementation a semiconductor memory device is provided in which each memory cell can store two bits of information. The memory device comprises a substrate, first and second buried bit lines in the substrate, a first bit line contact on the first buried bit line, a second bit line contact on the second buried bit line, and an insulator region disposed in the substrate between the first buried bit line and the second buried bit line. The insulator region prevents a current from flowing between the first buried bit line and the second buried bit line.

Dual-bit memory device having trench isolation material disposed near bit line contact areas

Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.

Methods for fabricating dual bit flash memory devices

A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a third dielectric layer formed over the second dielectric layer. The third dielectric layer may have a high dielectric constant and may be deposited at a relatively high temperature. A control gate may be formed over the third dielectric layer.

Non-volatile memory device with improved erase speed

Growing community of inventors

Santa Clara, CA, United States of America

Wei Zheng