Sandisk Technologies Inc.

Samsung Electronics Co., Ltd.

Western Digital Technologies, Inc.

Maxim Integrated Products, Inc.

Wei Zhao

Yingda Dong

Hong-Yan Chen

Ching-Huang Lu

Henry Chin

Yanli Zhang

Raghuveer S Makala

James K Kai

Rahul Sharangpani

Jiahui Yuan

George Matamis

Sateesh Koka

Deepanshu Dutta

Jayavel Pachamuthu

Huai-Yuan Tseng

Henry Chien

Ashish Kumar Baraskar

Zhenyu Lu

Johann Alsmeier

Jian Feng Chen

Xiang Yang

Albert M Bergemont

Peter Rabkin

Senaka Kanakamedala

Yi He

Abhijith Prakash

Wentao Wu

Peng Zhang

Somesh Peri

Fnu Vikram Singh

Han-Ping Chen

Wenguang Shi

Yong Yang

Glenn Yu

Chao Yang

Dong-il Moon

Sean Lynch

Che-Ping Chen

Xiaoyi Zhang

Hiroyuki Ogawa

Christopher John Petti

Gerrit Jan Hemink

Man Lung Mui

Liang Li

Tong Zhang

Yao-Sheng Lee

Dengtao Zhao

Mohan Dunga

Masanori Tsutsumi

Anubhav Khandelwal

Larry Lingjer Wang

Hua-Ling Cynthia Hsu

Andrew C Lin

Zhengyi Zhang

Vinh Diep

Fanglin Zhang

Larry Yu Wang

Xuan Tian

Takaaki Iwai

Charles S Kwong

Sayako Nagamine

Shigehiro Fujino

Lei Lin

Erika Penzo

Piyush Dak

Vincent Yin

Jiyin Xu

Xiaolong Hu

Koji Miyata

Dong-Il Moon

Makoto Koto

Dong-II Moon

Tony Zou

Stanley Jeong

Yuichi Ikezono

A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: during a program loop for programming a set of states, select a first bitline biasing mode that dictates a scheme for biasing a first set of bitlines and apply the first bitline biasing mode before verifying the set of states. The controller further configured to during another program loop for programming another set of states, select a second bitline biasing mode that dictates a scheme for biasing a second set of bitlines and apply the second bitline biasing mode before verifying the other set of states.

Hybrid precharge select scheme to save program ICC

The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.

Memory device with unique read and/or programming parameters

A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find first instruction.

Systems, methods, and devices for queue availability monitoring

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.

Read pass voltage dependent recovery voltage setting between program and program verify

The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.

Techniques for checking vulnerability to cross-temperature read errors in a memory device

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.

Temperature-dependent word line voltage and discharge rate for refresh read of non-volatile memory

Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

Digital temperature compensation filtering

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

Three-dimensional memory device containing plural work function word lines and methods of forming the same

Apparatuses and techniques are described for pre-charging NAND string channels in a pre-charge phase of a program operation. In one aspect, a hole-type pre-charge process is used at the source end of a NAND string, where a bottom of the NAND string is connected to a p-well of a substrate. By applying a positive voltage to the p-well and a lower voltage, such as 0 V or a negative voltage, to the source-side select gate transistors and the memory cells, the holes from the p-well are injected into the channel In another approach, the hole-type pre-charge process and an electron-type pre-charge process are used sequentially in separate time periods. In another approach, the hole-type pre-charge process is used at the source end of a NAND string while the electron-type pre-charge process is used at the drain end of the NAND string.

NAND string pre-charge during programming by injecting holes via substrate

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

Three-dimensional memory device with drain-select-level isolation structures and method of making the same

Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.

Method of reducing injection type of program disturb during program pre-charge in memory device

Techniques are described for maintaining a pre-charge voltage in a NAND string in a program operation. After a pre-charge voltage is applied to the channel of a NAND string, the word line voltages are controlled to avoid a large channel gradient which generates electron-hole pairs, where the electrons can pull down the channel boosting level on the drain side of the selected word line. In one approach, the word line voltages of a group of one or more source side word lines adjacent to the selected word line are increased directly from the level used during pre-charge to a pass voltage. The word line voltages of other source side word lines, and of drain side word lines, can be decreased and then increased to the pass voltage to provide a large voltage swing which couples up the channel.

Maintaining channel pre-charge in program operation

Growing community of inventors

Fremont, CA, United States of America

Wei Zhao