General Electric Company

China Unionpay Co., Ltd.

Covidien LP

Fudan University

Sabic Global Technolgoies B.v.

Dell Products Inc.

Chinese Academy of Sciences

Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Other

Basf Se Corporation

Delta Electronics, Inc.

Innogrit Technologies Co., Ltd.

Cytiva Bioprocess R&d Ab

Sabic Innovative Plastics IP B.v.

Wei Zhang

Qingqing Sun

Liping Zheng

Hai Yang

Wei Cai

Su Lu

Zhigang Deng

Xin Wang

Hui Liu

Zhijun Lu

Peng Fei Yi

Bing Zhang

Jingkang Shen

Zhou Hong

Ting Yu

Xiao Xun Zhang

Pengfei Wang

Wenqing Peng

Jun Sun

Rui Chen

Dake Shen

Tong Sun

Yun Zheng

Jianping Ying

Feng Han

Haiyang Zhang

Shiann-Ming Liou

Ying Chu Wang

Xu Wang

Feng Wang

Ying Nan Li

Jun Hou

Gang Zhao

Xiliang Zhang

Jie Gao

Wen Wen Yang

Rihua Xiong

Ryan W Rindy

Jun Zhu

Kun Zhao

Peng Zhou

Kitchener Clark Wilson

Tobias Soderman

Hui Lei

Ke Yu

Ying Li

Tianhua Ding

Yiming Zhu

Liming Yu

Hui Zhan

Fei Zhang

Wei Hu

Sen Yang

Yanming Yang

Bao Zhu

Shunhong Xu

Tao Meng

YuFei Zhang

Xiao Zhuang

Jinzhi Hua

Lanping Ma

Yanju Wang

Klaus Hochleitner

ChengKun Sun

Xianguo Yu

Yuming Mao

Rong Hou

Hongtao Shi

Longsheng Cai

ChengPing Luo

HaiChuan Wang

Bing Guan

Yida Xu

Damao Gong

Songlin Zhuang

Jiangfeng Zhang

Junhao Zhang

Zhiqiang Jiang

Yuandong Tan

Xiaowen Sun

Qin Zheng

Shouwei Li

Xiaoming Zhang

Yongliang Zhang

Yezhou Wu

Jintan Wu

Hongli Peng

Zhida Pan

Huanbing Wang

Ying Wang

Encheng Hu

Fen Du

Yanwen Bai

Jianyun Liu

Mingna Xiong

Chunjie Zhang

Yanrong Zhu

Ziyu Liu

Zhenke Wei

The application provides a data encryption and decryption method, device, storage medium, and encrypted file, and relates to the technical field of data processing. The method for data encryption includes: obtaining a first key, and performing an obfuscation operation on the first key and data to be encrypted to obtain obfuscation operation result data; obtaining a second key, and obtaining a first signature of the obfuscation operation result data according to the second key; obtaining a third key, and encrypting the first key, the data to be encrypted and the first signature using the third key to obtain a target ciphertext; obtaining a fourth key, and obtaining a second signature of the target ciphertext according to the fourth key; generating an encrypted file including the target ciphertext and the second signature. With the technical solutions of the application, security of data protection can be improved.

Data encryption and decryption method, device, storage medium and encrypted file

The invention provides an entrusted-authorization system and an entrusted-authorization method. The entrusted-authorization system comprises an accounting system, a switch module and an entrusted-authorization module, wherein the entrusted-authorization module stores entrusted-authorization parameters determined by the accounting system, the switch module is connected with the accounting system and the entrusted-authorization module for transmitting transaction request messages from the client terminal to the entrusted-authorization module for processing in case that the accounting system is unavailable, wherein the entrusted-authorization module verifies the transaction request messages according to the entrusted-authorization parameters; otherwise, the messages are sent to the accounting system for processing. The transaction request messages comprise financial account information, financial institution information, transaction-initiation institution information and transaction amount. With the entrusted-authorization system and entrusted-authorization method of the invention, a normal processing of transaction request can be ensured when the accounting system is unavailable.

Stand-in authorization system and stand-in authorization method

The present application discloses a method, an apparatus, a device for controlling traffic limitation and a storage medium, and belongs to the field of data processing. The method for controlling traffic limitation includes: acquiring, in response to a present request, a first timestamp of the present request; acquiring a pre-created traffic limitation instance, the traffic limitation instance including N storage blocks, a total number of instance requests, a traffic limitation request threshold number, an identifier of a storage block for a previous request, a second timestamp of the previous request and request waiting time; updating the traffic limitation instance based on a time interval between the first timestamp and the second timestamp, the unit time length, and the traffic limitation request threshold number; and determining whether to perform traffic limitation based on the request waiting time in the updated traffic limitation instance.

Method, apparatus and device for controlling traffic limitation and storage medium

A surgical stapling device includes a staple reload and a handle assembly that supports a drive rack, a motor assembly, a gear assembly, a reload select mechanism, and a safety toggle mechanism. The gear assembly is adapted to facilitate uncoupling of the motor assembly from the drive rack to allow manual movement of the drive rack. The reload select mechanism allows the length of a stroke of the drive rack to be selectively adjusted to allow the stapling device to accommodate different length staple reloads. The safety toggle mechanism is provided to move the stapling device from a non-firing state to a firing state to allow for firing of the stapling device.

Surgical stapling device with powered handle assembly

The present disclosure discloses a three-dimensional integration system of an RFID chip and a supercapacitor and a manufacturing method thereof. The three-dimensional integration system of an RFID chip and a supercapacitor includes: a silicon substrate (); an RFID chip () disposed on a front surface of the silicon substrate (); a supercapacitor disposed on a back surface of the silicon substrate () at a position corresponding to the RFID chip (), but not in contact with the RFID chip (); through silicon via structures penetrating the silicon substrate () and respectively disposed on two sides of the RFID chip (); wherein the RFID chip () has a chip positive electrode () and a chip negative electrode () electrically connected with a capacitor contact positive electrode () and a capacitor contact negative electrode () of the supercapacitor through the through silicon via structures on the two sides respectively; and a packaging substrate () electrically connected to the capacitor contact positive electrode () and the capacitor contact negative electrode ().

Three-dimensional integrated system of RFID chip and super capacitor and preparation method thereof

An information processing method, an interconnection device, and a computer-readable storage medium are provided. The interconnection device includes a request processing module configured for: receiving a data access request from at least one processor, wherein the data access request comprises a merge bit, a multicast group identifier (MGID), and a multicast transaction identifier (MTID); determining whether the data access request is a multicast request; determining whether the interconnection device receives other multicast requests if it is determined that the data access request is a multicast request based on the MGID, the MTID, and a static routing policy of a multicast group; and obtaining the other multicast requests if it is determined that the interconnection device receives the other multicast requests, merging the multicast request with the other multicast requests into a merged request, and forwarding the merged request to a next-hop device of the interconnection device.

Interconnection device

The present disclosure provides to a processing device and a processing method for a ray tracing acceleration structure. The processing device includes a machine-readable storage medium and a processor. The processor executes a descriptor to simulate the interaction between the ray with the scene, and the descriptor includes a first pointer and a second pointer. The processor obtains the TLAS by using the first pointer. The processor traverses the TLAS to find a leaf node in the TLAS that intersects the ray, and the intersected leaf node includes an instance identifier. The processor obtains the intersected instance record from the instance buffer pointed to by the second pointer by using the instance identifier, and the intersected instance record includes a third pointer. The processor obtains the BLAS by using the third pointer. The processor traverses the BLAS to find a primitive node in the BLAS that intersects the ray.

Processing device and processing method for ray tracing acceleration structure

Disclosed are a new AXL-targeting monoclonal antibody and antibody-drug conjugate. Also disclosed is a method for preparing said antibody and antibody-drug conjugate. The AXL antibody of the present invention can bind with purified human AXL protein and multiple AXL on tumor cell surface with high effectiveness and high specificity. Said humanized antibody also has high affinity and low immunogenicity. Said AXL antibody-drug conjugate has markable performance against tumors having high AXL expression.

AXL-targeting antibody, antibody-drug conjugate, preparation method therefor, and use thereof

The embodiments of the disclosure relate to a computing device, a computing equipment, and a programmable scheduling method for data loading and execution, and relate to the field of computer. The computing device is coupled to a first computing core and a first memory. The computing device includes a scratchpad memory, a second computing core, a first hardware queue, a second hardware queue and a synchronization unit. The second computing core is configured for acceleration in a specific field. The first hardware queue receives a load request from the first computing core. The second hardware queue receives an execution request from the first computing core. The synchronization unit configured to make the triggering of the load request and the execution request to cooperate with each other. In this manner, flexibility, throughput, and overall performance can be enhanced.

Computing device, computing equipment and programmable scheduling method

Disclosed is a method for the recovery of nucleic acids from a solid support, the method comprising the steps, in any suitable order, of: a) providing a solid support at least a region of which is absorbent and impregnated with a chaotropic agent; b) combining a biological sample, possibly including nucleic acids, with the region; c) washing the region in a washing buffer solution; d) simultaneously heating and agitating the region in a further buffer solution; e) separating the region from the further buffer solution; f) extracting at least a portion of any remaining further buffer solution from the region to provide an extracted buffer solution; g) combining the further buffer solution and the extracted buffer solution portion; and h) subsequently processing the combined buffer solutions in order to amplify any nucleic acids in said combined solution. Hardware suitable for implementing the above method and a kit of parts is disclosed also.

Recovery of nucleic acids from solid supports

The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof. The method of the present disclosure includes the following steps: lifting off a silicon wafer by implanting hydrogen ions into the silicon wafer to obtain a substrate for making a through silicon via; performing double-sided plasma etching on the substrate to form a through silicon via penetrating the substrate; depositing an insulating medium, a copper diffusion barrier layer, and a seed layer; and removing parts of the copper diffusion barrier layer and the seed layer by photolithography and etching processes, leaving only parts of the copper diffusion barrier layer and the seed layer on a sidewall of the through silicon via; forming a sacrificial layer on the upper and lower surfaces of the resulting structure, completely filling in the through silicon via with conductive metal material, and then removing the sacrificial layer, upper and lower surfaces of the conductive metal material respectively protruding from upper and lower surfaces of the insulating medium; and forming a contact pad on a surface of the conductive metal material. The present disclosure can effectively improve production efficiency and lower the cost.

Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof

The present disclosure provides a method and a device for transaction clearing. The method includes receiving first clearing requests transmitted by a quantity N of terminals, where N>1; according to the first clearing requests, acquiring transaction data of the quantity N of terminals from a database; initializing a cache queue, and loading the transaction data into the cache queue; reading the transaction data in the cache queue, and performing a clearing process on the transaction data; and writing a clearing result into the database and feeding back the terminals with an execution result of the first clearing requests.

Transaction settlement method and apparatus

Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.

SOI active transfer board for three-dimensional packaging and preparation method thereof

The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method, The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer; and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor, The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the same time can integrate capacitors and inductors near the chip in three-dimensional integration, and can also improve the functional density of through silicon via in three-dimensional integration and increase the utilization rate of silicon in system integration. Compared with discrete capacitors and inductors on other organic substrates, the integration can be greatly improved.

Three-dimensional capacitor-inductor based on high functional density through silicon via structure and preparation method thereof

Information processing method, interconnection device and computer-readable storage medium

Growing community of inventors

Shanghai, China

Wei Zhang