Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Wei Zhang

Yong Liu

Jun Cao

Seong-Ho Lee

Hyung-Joon Jeon

Angus Tang

SangHye Chung

Mohammed Mohsen Abdul-Salam Abdul-Latif

Vadim Milirud

A system includes a dither generator module that includes a most significant bits (MSB) dither generator device that generates a first random value. The dither generator module also includes a least significant bits (LSB) dither generator device that generates a second random value. The system further includes a first digital to analog converter (DAC) that receives a sum of the first random value and the second random value and generates a dither signal based on the sum of the first random value and the second random value. The system also includes an analog to digital converter (ADC) that receives a sum of the dither signal and a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to produce a digitized output signal.

Split-dithering scheme in successive approximation analog to digital converter

An apparatus includes control logic coupled to a phase detector circuit and an adjustable delay circuit. The control logic is configured to obtain a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, and adjust a delay of the reference signal until the second phase matches the first phase. The control logic is further configured to measure a total delay of the reference signal when the second phase matches the first phase, and determine integral non-linearity of the phase interpolator at the first code based on the total delay. The control logic may further calibrate a first code of a phase interpolator based, at least in part, on the integral non-linearity.

INL detection and calibration for phase-interpolator

A differential driver circuit includes a differential driver configured to drive an output signal based upon a positive leg pull up signal, a positive leg pull down signal, a negative leg pull up signal, and a negative leg pull down signal. A first pre-driver includes a first driver configured to receive a positive leg signal and a first voltage divider coupled to an output of the first driver and configured to produce the first pull up signal and the first pull down signal. A second pre-driver includes a second driver configured to receive a negative leg signal and a second voltage divider coupled to an output of the second driver and configured to produce the second pull up signal and the second pull down signal. The differential driver may include a positive leg and a negative leg, each having a pull up transistor and a pull down transistor.

Differential driver circuit having bias equalizing pre-drivers

Methods and apparatuses for high rotation rate low I/O count phase interpolation are disclosed, including techniques to reduce redundant phase interpolation coding and method steps by modifying phase mapping and generation with pluralities of amplifiers. I/O reduction count is achieved while maintaining resolution and allowing scalability in phase interpolation. Control circuits include techniques to interpolate phases at a high rotation rate while reducing discontinuities and risk for logic hazards.

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Irvine, CA, United States of America

Wei Zhang