National Yang Ming Chiao Tung University

Industrial Technology Research Institute

Realtek Semiconductor Inc.

Novatek Microelectronics Corp.

National Central University

Princeton Technology Corporation

Wei-Zen Chen

Yao-Chia Liu

Yu-Ping Huang

Zheng-Hao Hong

Chih-Jen Yen

Chung-Yu Wu

Yu-Hsiang Chen

Li-Ren Huang

Song-Yu Yang

I-Te Liu

Day-Uei Li

Chi-Wei Yen

Hsin-Pei Lee

Shu-Chin Chuang

Chia-Tse Hung

Yan-Ting Wang

Chun-Pao Lin

Chi-Yao Yu

Guan-Sheng Huang

Dar-Huei Liao

Shih-Hsuan Hung

Wen-Hui Chen

Yau-Chia Liu

Yu-Sian Liao

Kuan-Hsiu Chien

Ming-Chiuan Su

A computing-in-memory apparatus is provided, which includes a voltage regulator having an amplifier and a reference current source, a computing-in-memory array having a plurality of computing units and a detection circuit connected to each other. The amplifier has a current input and a voltage output and is connected to the reference current source, and the voltage regulator provides an output voltage for supplying to the computing-in-memory array. An output current of the detection circuit is inputted into the voltage regulator to compare with the reference current source of the voltage regulator, and then a negative feedback convergence or a negative feedback mechanism is executed according to the comparison result to regulate the output voltage supplied by the voltage regulator to the computing-in-memory array.

Computing-in-memory apparatus

A system of referenceless clock and data recovery and a frequency detector thereof has been provided. The output clock of the system initially works at the lowest frequency, the frequency of the output clock is monotonically increased in accordance with the control of the frequency detector, thereby gradually approximating a target value. The edge extraction circuit receives the data signal and the clock signal, identifies the transition edges of the signals and generates a data transition signal and a clock transition signal representing the transition edges of the data signal and the transition edges of the clock signal respectively. The edge detector then determines the data period of the data signal and the clock period of the clock signal. When the data period is smaller than half of the clock period, the edge detector generates a frequency-up signal and the frequency of the output clock is increased.

System of referenceless clock and data recovery and frequency detector thereof

A clock data recovery circuit includes: a first detecting circuit for detecting phases of an incoming data signal and a sampling clock signal to generate a first detection signal; a loop filter for generating a control signal according to the first detection signal; a second detecting circuit for detecting phases of a reference signal and a feedback signal to generate a second detection signal; a control voltage generating circuit for generating a control voltage based on the second detection signal; a voltage-controlled oscillator for generating the sampling clock signal according to the control voltage; a phase adjustment circuit for adjusting the phase of the sampling clock signal according to the control signal to generate the phase-adjusted signal; and a frequency divider circuit for conducting a frequency division operation on the phase-adjusted signal to generate the feedback signal.

Clock data recovery circuit

A wireless receiving device includes a wake-up receiver, a main receiver and a calibration circuit. The wake-up receiver operates in a monitoring mode or a sleep mode. When operating in the monitoring mode, the wake-up receiver monitors whether a request signal is transmitted by a communication device and issues a wake-up signal after receiving the request signal. The main receiver operates in a sleep mode or a transmission mode. When operating in the sleep mode, the main receiver is woken up and enters the transmission mode to transmit and receive data to and from the communication device when receiving the wake-up signal. The calibration circuit is coupled to the wake-up receiver and the main receiver and configured to receive a calibration signal from the main receiver and calibrate a reception frequency of the wake-up receiver in the background in response to the calibration signal.

Wireless receiving device, wake-up receiver and method for calibrating a frequency and a bandwidth

A multi-level pulse-amplitude modulation receiver system includes an analog equalizer, a digital equalizer, an automatic level tracking engine and an automatic gain controller. The analog equalizer and the automatic gain controller perform signal compensation on a multi-bit quasi-attenuation signal to generate a multi-level compensation signal. The digital equalizer receives the multi-level compensation signal, the positive threshold voltage and the negative threshold voltage, and thereby converts the multi-level compensation signal into a plurality of digital data. The automatic level tracking engine uses the digital data to generate a positive threshold voltage, a negative threshold voltage, at least two positive DC level voltages, and at least two negative DC level voltages, and the positive threshold voltage is an average of the two positive DC level voltages to avoid the nonlinear effect of the analog front end.

Multi-level pulse-amplitude modulation receiver system

A readout circuit of a touch panel is provided. The readout circuit includes a charge modulator and a correlated double sampling demodulator. The charge modulator is configured to provide a driving current to charge or discharge a sensing electrode of the touch panel and generate a sensing voltage signal. The correlated double sampling demodulator is coupled to the charge modulator. The correlated double sampling demodulator is configured to sample the sensing voltage signal to obtain a voltage variation when a touch event happens. A method for driving the touch panel is also provided.

High sensitivity readout circuit for touch panel

A frequency synthesizer and a method for frequency synthesis are provided. The frequency synthesizer includes a subband phase-locked loop (PLL) and a main PLL. A divisor of an adjustable non-integer frequency divider in the subband PLL is adjusted, and a channel frequency of a maximum frequency band of all frequency bands is output. A divisor of an adjustable integer frequency divider in the main PLL is adjusted, and a center frequency required for each frequency band of the all frequency bands is output. The center frequency and the channel frequency are mixed by a mixer to produce a band frequency. A quantization noise generated by the adjustable non-integer frequency divider is filtered out by the subband PLL to reduce the impact of the quantization noise on the main PLL.

Frequency synthesizer and method for frequency synthesis

A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.

Phase detecting device and clock data recovery circuit embedded with decision feedback equalizer

A low voltage quadrature phase wideband relaxation oscillator. An ultra-wideband tuning range from Mega to Giga Hz order is also realized by tuning the I/Q coupling factor, zeros and poles. Preferably, a novel synchronous quadrature injection lock is proposed to validate low noise performance.

Quadrature phase relaxation oscillator

An exemplary clock and data recovery circuit includes a serial data input node arranged for receiving a serial data; a reference clock input node arranged for receiving a reference clock; a control circuit arranged for generating a control signal to selectively configure the clock and data recovery to operate in one of a plurality of phases; a detective circuit arranged for generating a first adjusting signal while the clock and data recovery operates in a frequency locking phase, and for generating a second adjusting signal while the clock and data recovery circuit operates in a clock and data recovery phase; and a controllable oscillator arranged for generating a recovered clock according to the first adjusting signal in the frequency locking phase, and for generating the recovered clock according to the second adjusting signal in the clock and data recovery phase.

Clock and data recovery circuit selectively configured to operate in one of a plurality of stages and related method thereof

The invention provides a phase-locked loop with loop gain calibration and methods for measuring an oscillator gain, gain calibration and jitter measurement for a phase-locked loop. The method for measuring an oscillator gain of a phase-locked loop includes the steps of providing a varying code at an input end of the oscillator; outputting excess reference phase information by a reference phase integral path and outputting excess feedback phase information based on the varying code by a feedback phase integral path; and obtaining an estimated gain information of the oscillator based on the excess reference phase information and the excess feedback phase information.

Phase-locked loop with loop gain calibration, gain measurement method, gain calibration method and jitter measurement method for phase-locked loop

The PLL includes a voltage-controlled oscillator (VCO), a frequency down conversion circuit, a phase-frequency detector (PFD), and an adjusting circuit. The VCO is configured to generate an output clock signal. The frequency down conversion circuit is configured to receive the output clock signal and an auxiliary clock signal, and to mix the output clock signal and the auxiliary clock signal to generate a feedback clock signal. By detecting the strength of the feedback clock signal, it provides an auxiliary signal to adjust the frequency of the output clock signal. The PFD is configured to compare the frequencies and the phases of the feedback clock signal and a reference clock signal to generate an adjusting signal. The adjusting circuit is configured to receive the adjusting signal, and to adjust the frequency of the output clock signal generated by the VCO according to the adjusting signal.

Phase-locked loop

An amplifier circuit includes a modulation signal generating circuit, a driving stage circuit and an output stage circuit. The modulation signal generating circuit generates a pair of modulation signals according to a pair of differential input signals and a pair of clock signals. The pair of clock signals includes a first clock signal and a second clock signal having a phase difference therebetween. The driving stage circuit generates a pair of driving signals according to the pair of modulation signals. The output stage circuit generates a pair of amplified output signals according to the pair of driving signals.

Amplifier circuits and modulation signal generating circuits therein

A voltage-controlled oscillator comprises a variable inductor, a negative impedance circuit, an operating voltage source and a ground point. The variable inductor comprises a transformer and a transistor switch, the transformer comprising a primary side coil and a secondary side coil, the primary side coil comprising a first coil and a second coil, and the secondary side coil comprising a third coil and a fourth coil. The transistor switch is connected in parallel with the primary side coil to adjust an inductance value of the variable inductor based on a gate voltage. The negative impedance circuit is connected in parallel with the secondary side coil to compensate the power consumption of the voltage-controlled oscillator during oscillation. The operating voltage source is electrically connected between the third coil and the fourth coil, and the ground point is electrically connected between the first coil and the second coil.

Voltage-controlled oscillator

A digital PLL frequency synthesizer characterized by fast-locking and low-jitters is presented. The PLL comprises a phase detector, a controllable oscillator, a loop filter having an automatically-adjusted loop gain, a feedback phase integration circuit, and a reference phase integration circuit. Fast-locking is achieved by dynamically adjusting forward-path gain and integral-path gain according to the output of the phase detector and the output of the integral-path during phase tracking. A skew-compensated counter circuit is proposed, which incorporates an asynchronous counter, a data register and a sample phase generator and features high-speed and low-power operation.

Growing community of inventors

Hsinchu, Taiwan

Wei-Zen Chen