The Mathworks, Inc.

Skhynix Inc.

Wei Zang

Girish Venkataramani

Wang Chen

Kiran K Kintali

Rajiv Ghosh-Roy

Katalin Maria Popovici

Chun Hok Ho

Abhijeet H Gadkari

Matthew H Fornero

Senthilkumar Manickavasagam

Memory systems may include a memory including a plurality of dies, and a controller suitable for receiving a host read request during programming of one of the plurality of dies; determining a suspendable die among the plurality of dies based on a suspension threshold; and suspending the determined suspendable die and performing the received request.

Controller adaptation to memory program suspend-resume

A method may include receiving functional model information regarding a set of functional blocks associated with a functional model. The functional model may include a streaming algorithm for exchanging streaming data. The method may include receiving architectural model information regarding physical devices included in a target device from a hardware-software co-design platform. The physical devices may include a software based processing device and a hardware based processing device. The method may include mapping the functional blocks to the physical devices to allow the streaming data to be communicated between the software based processing device and the hardware based processing device. The method may include generating a streaming interface to model communication of the streaming data between the software based processing device and the hardware based processing device. The method may include generating computer code for implementing the functional model on the target device and outputting the computer code.

Streaming on hardware-software platforms in model based designs

Systems and methods optimize hardware description generated from a graphical model automatically. The system may include an optimizer. The optimizer may add a serializer component and a deserializer component to the model. The serializer component may receive parallel data and may produce serial data. The serializer may introduce one or more idle cycles into the serial data being produced. The deserializer component may receive serial data and may produce parallel data. The serializer and deserializer components may receive and generate control signals. The control signals may include a valid signal for indicating valid data elements of the serial and parallel data, and a start the start signal for indicating the beginning of a new frame or cycle when constructing parallel data from serial data.

Systems and methods for optimizing executable models for hardware synthesis

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Wei Zang