Phison Electronics Corporation

Wei-Yung Chen

Chih-Ming Chen

Sheng-Wen Chen

Jen-Chu Wu

Yu-Chiang Liao

Wei-Ting Wei

Ming-Hui Tseng

An-Chung Chen

Wen-Lung Cheng

Yu-An Chen

Chia-Hui Yu

Wei-Shin Chang

Shin-Yang Sun

Chao-Hsin Lin

Yan-An Lin

A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and detecting the third signal to calibrate an electronic parameter of the phase-locked loop circuit.

Phase-locked loop circuit calibration method, memory storage device and connection interface circuit

An exemplary embodiment of the disclosure provides a switch module which includes a first conductive unit, a first switch unit and a first electrostatic protection module. The first electrostatic protection module is coupled between the first conductive unit and the first switch unit. The first electrostatic protection module includes a first protection circuit and a first inductor circuit. The first inductor circuit includes a first inductor unit, and the first inductor circuit is coupled between the first protection circuit and the first conductive unit. Accordingly, the transmission efficiency of the switch (or multiplexer) for high speed signal can be improved.

Switch module, memory storage device and multiplexer

An equalizer tuning method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type parameter and modulating the first signal by a second modulation circuit according to a second type parameter; detecting a signal eye-width value and a signal eye-height value of the modulated first signal; and adjusting the first type parameter according to the detected signal eye-width value and adjusting the second type parameter according to the detected signal eye-height value.

Equalizer tuning method, signal receiving circuit and a memory storage device

A sampling circuit module, a memory control circuit unit, and a data sampling method, where the sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.

Sampling module including delay locked loop, sampling unit, memory control unit, and data sampling method thereof

An exemplary embodiment provides an equalizer adjustment method. The method includes: performing a handshake operation to establish a connection with a host system by a memory storage device; in the handshake operation, receiving a first signal from the host system and performing a first modulation on the first signal by the adaptive equalizer; after the handshake operation is ended, receiving a second signal from the host system and performing a second modulation on the second signal according to a modulation result of the first modulation by the adaptive equalizer to compensate the second signal; and adjusting the adaptive equalizer according to a modulation result of the second modulation.

Equalizer adjustment method, adaptive equalizer and memory storage device

An eye-width detector, a memory storage device and an eye-width detection method of data signal are provided. The eye-width detector includes a phase interpolator, a calibration circuit and an eye-width detection circuit. The phase interpolator receives a first clock signal and a phase control signal and output a second clock signal. The calibration circuit receives the first clock signal and the second clock signal and output a first control signal. The eye-width detection circuit receive the data signal, the first clock signal and the second clock signal and generate a first sampling value and a second sampling value. If the first sampling value and the second sampling value do not match a first condition, the eye-width detection circuit outputs a second control signal; otherwise, outputs eye-width information of the data signal. Accordingly, the efficiency of the eye-width detection may be improved.

Eye-width detector, memory storage device and eye-width detection method of data signal

A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.

Phase lock method

A clock and data recovery circuit module and a phase lock method are provided. The module includes a phase detection circuit, a converter circuit and a voltage control oscillation circuit. The phase detection circuit is configured to detect a phase difference between a data signal and a feedback clock. The converter circuit is coupled to the phase detection circuit and configured to output a first phase control voltage and a second phase control voltage according to the phase difference. The voltage control oscillation circuit is coupled to the converter circuit and configured to receive the first phase control voltage and the second phase control voltage and output the feedback clock according to the first phase control voltage and the second phase control voltage.

Clock and data recovery circuit module and phase lock method

A memory storage device having a clock and data recovery circuit module are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.

Memory storage device having clock and data recovery circuit

A signal modulation method, an adaptive equalizer and a memory storage device are provided. The method includes: receiving a first signal; performing a first modulation on the first signal based on a first power mode to generate a second signal having a first eye-width; performing a second modulation based on a second power mode to generate the second signal having a second eye-width; determining whether the first eye-width and the second eye-width meet a first condition; if yes, performing a third modulation based on the first power mode to generate the second signal having a third eye-width; otherwise, performing the third modulation based on the second power mode to generate the second signal having the third eye-width. Therein, a power consumption of performing the second modulation is less than that of performing the first modulation. Therefore, an efficiency of the adaptive equalizer may be improved.

Signal modulation method, adaptive equalizer and memory storage device

A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating a sensing voltage pair according to the differential signal, where the sensing voltage pair includes a first sensing voltage and a second sensing voltage, a voltage value of the first sensing voltage is related to a first differential signal of the differential signal, and a voltage value of the second sensing voltage is related to a second differential signal of the differential signal; and receiving the sensing voltage pair and outputting a sampling data stream according to a clock of the differential signal and a voltage relative relationship of the sensing voltage pair.

Data sampling circuit module, data sampling method and memory storage device

A memory storage device, a memory control circuit unit, and a clock adjusting circuit disposed on a plurality of layers are provided. The clock adjusting circuit includes a detection circuit, a control voltage generating circuit, and a voltage-controlled oscillator (VCO). The detection circuit detects a signal characteristic difference between an input signal and an output signal to generate a first signal. The control voltage generating circuit is coupled to the detection circuit and generates a control voltage according to the first signal. The VCO is coupled to the control voltage generating circuit and includes an inductor and a capacitor. The VCO receives the control voltage and starts oscillating according to an impedance characteristic of the inductor and the capacitor to generate the output signal. The inductor is disposed on a pad layer among the layers. Thereby, the manufacturing cost is reduced.

Clock adjusting circuit, memory storage device, and memory control circuit unit

A connecting interface unit and a memory storage device without a crystal oscillator are provided and include a frequency detector, a phase detector, an oscillator, a sampling circuit and a transmitter circuit. The frequency detector and the phase detector respectively detect frequency difference and phase difference between an input signal from a host system and a reference signal to generate a frequency signal and a phase signal. The frequency signal and the phase signal that have passed through a filter are transmitted to the oscillator to generate the reference signal for generating a clock signal. The sampling circuit generates an input data signal according to the reference signal. The transmitter circuit modulates an output data signal according to the clock signal to generate and transmit an output signal to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission stand.

Connecting interface unit and memory storage device

A controlling method for connector is provided, which includes: receiving a first signal stream under a condition that a squelch detector is turned-off; determining whether the first signal stream contains a burst signal under a first operating frequency; if the first signal stream contains the burst signal, turning on the squelch detector and determining by the squelch detector under a second operating frequency whether a second signal stream is a waking signal, wherein the second signal stream is received after receiving the first signal stream and the second operating frequency is greater than the first operating frequency. The controlling method further includes: if the second signal stream is the waking signal, changing an operating state of the connector to an active state. In this way, the power consumption of the connector is reduced.

Controlling method for connector, connector and memory storage device

A connecting interface unit and a memory storage device without a crystal oscillator are provided and include following circuits. A phase detector detects a phase difference between a first reference signal and an input signal from a host system to generate a phase signal. A signal detecting circuit detects a signal character difference between the input signal and the first reference signal for a signal generating circuit to generate a second reference signal. A phase interpolator generates a clock signal according to the phase signal and the second reference signal. A sampling circuit generates an input data signal according to the clock signal. A transmitter circuit modulates an output data signal according to the clock signal or the second reference signal to generate an output signal, and transmits it to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission standard.

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Hsinchu County, Taiwan

Wei-Yung Chen