Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Wei Yu Ma

Kuo-Ji Chen

Fang-Tsun Chu

Kvei-Feng Yen

Yao-Bin Wang

Chia-Hui Chen

Li-Chun Tien

Ta-Pen Guo

Bo-Ting Chen

Ting Yu Chen

Hsien-Wei Chen

Hao-Yi Tsai

An integrated circuit includes two or more substrates stacked one over another and a first set of electrical components on one or more of the two or more substrates. The two or more substrates include a first substrate having a first predetermined doping type and a second substrate having the first predetermined doping type. The first set of electrical components is configured to form a first circuit. The integrated circuit further includes a first ground reference rail electrically connected to the first circuit, a first common ground reference rail, and a first ESD conduction element electrically connected between the first ground reference rail and the first common ground reference rail. The first ESD conduction element includes a first diode on the first substrate and a second diode on the second substrate. The first diode and the second diode are electrically connected in parallel and have opposite polarities.

Three-dimensional integrated circuit having ESD protection circuit

A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics

A method (of forming an integrated circuit) includes: forming a first diode on a first substrate of two or more stacked substrates, the first substrate having a first predetermined doping type; forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed on the first substrate, and the second substrate having the first predetermined doping type; and forming conductive paths electrically connecting the first diode 3A and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities.

Method of forming three-dimensional integrated circuit having ESD protection circuit

An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration

One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements include a first substrate, a second substrate, an ESD pad, an ESD device and a first interlayer via connecting the first substrate and the second substrate. The first substrate includes a first PMOS device and a first device and the second substrate includes a first NMOS device and a second device. Alternatively, the first substrate includes a first PMOS device and a first NMOS device and the second substrate includes a first device and a second device.

Semiconductor arrangement with electrostatic discharge (ESD) protection

A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vand V.

Semiconductor device with seal ring with embedded decoupling capacitor

A circuit with an electro-static discharge clamp coupled to a first power source and second power source. The electro-static discharge clamp includes an NMOS stack and an electro-static discharge detector. The NMOS stack has a first NMOS transistor with a first gate node and a second NMOS transistor with a second gate node. The electro-static discharge detector is configured to control the NMOS stack, and may include three switches. A first switch is configured to switch the first gate node to the second power source. A second switch is configured to switch the first gate node to the second gate node. A third switch is configured to switch the first gate node to the ground.

Self biased electro-static discharge clamp (ESD) for power rail

Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.

Failsafe ESD protection

The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.

Semiconductor integrated circuit having a resistor and method of forming the same

A circuit with an electro-static discharge clamp coupled to a first power source and second power source. The electro-static discharge clamp includes an NMOS stack and an electro-static discharge detector. The NMOS stack has a first NMOS transistor with gate node ngand a second NMOS transistor with gate node ng. The electro-static discharge detector is configured to control the NMOS stack, and may include three switches. A first switch is configured to switch the gate node ngto the second power source. A second switch is configured to switch the gate node ngto the gate node ng. A third switch is configured to switch the gate node ngto the ground.

Growing community of inventors

Taitung, Taiwan

Wei Yu Ma