Taiwan Semiconductor Manufacturing Comp. Ltd.

Asustek Computer Inc.

Epistar Corporation

Hon Hai Precision Industry Co., Ltd.

Innovative Sonic Corporation

Inventec Corp.

National Yang Ming Chiao Tung University

Hewlett-packard Development Company, L.p.

3m Innovative Properties Company

Mediatek Corporation

Tsinghua University

Molex Corporation

Wistron Corporation

Chung Yuan Christian University

National Chung Shan Institute of Science and Technology

Wei-Yu Chen

Chung-Shi Liu

An-Jhih Su

Hsiu-Jen Lin

Hsien-Wei Chen

Ming-Da Cheng

Ching-Hua Hsieh

Chen-Hua Douglas Yu

Li-Hsien Huang

Der-Chyang Yeh

Li-Te Pan

Hao-Jan Pei

Li-Chih Tseng

Chia-Shen Cheng

Chih-Chiang Tsao

Chi-Hsi Wu

Ming-Che Li

Cheng-Ting Chen

Chia-Lun Chang

Wei-Hung Lin

Hsiang-Jen Tseng

Hsuan-Ting Kuo

Ting-Wei Chiang

Kuei-Wei Huang

Yu-Hsiang Hu

Philip Yu-Shuan Chung

Li-Chun Tien

Tien-Chung Yang

Richard Lee-Chee Kuo

Kuan-Lin Ho

Shih-I Chen

Ming-Shih Yeh

Ching-Pei Lin

Hung-Jui Kuo

Jiun Yi Wu

Meng-Tse Chen

Yu-Min Liang

Yu-Peng Tsai

Ying-Ju Chen

Wen-Hsiung Lu

Chin-Liang Chen

Jiun-Yi Wu

Chi-Yang Yu

Yu-min Liang

Chih-Wei Lin

Po-Hao Tsai

Wei-Cheng Wu

Chien-Hsun Lee

Yu-Hsuan Guo

Tsung-Ding Wang

Tsung-Shu Lin

Chien-Fu Huang

Yi-Ming Chen

Cheng-Hsien Hsieh

Chin-Chuan Chang

Chien-Wei Lee

Tsung-Xian Lee

Jung-Wei Cheng

Chen-Fa Lu

Hui-Zhong Zhuang

Kuo-Nan Yang

Chia-Liang Hsu

Ta-Pen Guo

Chun-Cheng Lin

Ming-Hsiang Song

Wen-Luh Liao

Ming Shih Yeh

Chun-Chih Chuang

Chih-Hua Chen

Chun-Wei Huang

Yu-Chih Huang

Hsin-Yu Pan

Shun Li Chen

Hao-Cheng Hou

Ai-Tee Ang

Tun-Huai Shih

Hua-Wei Tseng

Hung-Ta Cheng

Yi-Da Tsai

Min-Hsun Hsieh

Kai-Chiang Wu

Li-Hui Cheng

Ming-Che Ho

Yu-Ting Lin

Chun-Lin Lu

Meng-Hui Ou

Shang-Chih Hsieh

Yu-Sheng Wang

Tzu-Chieh Hsu

Hsin-Mao Liu

Yi-Hsuan Kung

Jia-Hong Liou

Tzu-Chun Tang

Chao-Kai Cheng

Yi-Ying Liu

Guang-Nan Tzeng

Yi-Sheng Kao

Cheng-Nan Han

Yi-Liang Hou

Chun-Fu Chen

A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Three-dimensional (3D) package

A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

Semiconductor device and method of manufacture

An in-process structure including an interposer is provided. The interposer includes first interposer bonding pads. An array of copper pillar structures is bonded to the first interposer bonding pads using interposer-side solder material portions. A packaging substrate is attached to the array of copper pillar structures by bonding the array of copper pillar structures to substrate bonding pads located on the packaging substrate using substrate-side solder material portions.

Package structure including an array of copper pillars and methods of forming the same

A method and apparatus are disclosed from the perspective of a first device. In one embodiment, the method includes the first device performs sensing on a data resource pool, and the first device selects/derives at least a first data resource from the data resource pool based on the sensing result of the data resource pool. The method further includes the first device transmits a first control information on a first control resource, wherein the first control information allocates or indicates the first data resource. The method also includes the first device performs a first data transmission on the first data resource to at least one second device. Furthermore, the method includes the first device determines or derives a first set of feedback resource(s) based on the first control resource and/or the first data resource; and the first device receives a first set of feedback transmission(s) on the first set of feedback resource(s) from at least the one second device, wherein the first set of feedback transmissions are associated with the first data transmission.

Method and apparatus of deriving feedback resource for sidelink transmission in a wireless communication system

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

Methods of forming semiconductor packages

A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

Semiconductor package and method

A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Die corner removal for underfill crack suppression in semiconductor die packaging

A substrate structure includes a core substrate, a redistribution layer, a plurality of test pads, a first protective coating, at least one conductive pad and a passive device. The redistribution layer is disposed on and electrically connected to the core substrate. The test pads are disposed over the redistribution layer. The first protective coating is coated on the test pads. The conductive pad is d disposed on the redistribution layer aside the plurality of test pads. The passive device is disposed on and electrically connected to the at least one conductive pad.

Probe card substrate, substrate structure and method of fabricating the same

A method of handling a workpiece includes the following steps. A workpiece is placed on a chuck body, wherein the workpiece includes a tape carrier extending beyond a periphery of the chuck body and a workpiece body disposed on the tape carrier, and the chuck body includes a seal ring surrounding the periphery of the chuck body; the tape carrier is clamped outside the chuck body, wherein the tape carrier leans against the seal ring and an enclosed space is formed between the chuck body, the tape carrier and the seal ring; and a vacuum seal is formed by evacuating gas from the enclosed space to pull the periphery of the workpiece toward the chuck body.

Method of manufacturing semiconductor package, method of handling wafer, and method of handling workpiece

A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.

Package structure with warpage-control element

A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

Semiconductor packages and methods of forming the same

A system for reflowing a semiconductor workpiece including a stage, a first vacuum module and a second vacuum module, and an energy source is provided. The stage includes a base and a protrusion connected to the base, the stage is movable along a height direction of the stage relative to the semiconductor workpiece, the protrusion operably holds and heats the semiconductor workpiece, and the protrusion includes a first portion and a second portion surrounded by and spatially separated from the first portion. The first vacuum module and the second vacuum module respectively coupled to the first portion and the second portion of the protrusion, and the first vacuum module and the second vacuum module are operable to respectively apply a pressure to the first portion and the second portion. The energy source is disposed over the stage to heat the semiconductor workpiece held by the protrusion of the stage.

Reflow method and system

A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Warpage control in the packaging of integrated circuits

A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.

Method of manufacturing semiconductor structure

A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Semiconductor structure and manufacturing method thereof

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Taipei, Taiwan

Wei-Yu Chen