Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-yu Chen

An-Jhih Su

Chen-Hua Douglas Yu

Der-Chyang Yeh

Li-Hsien Huang

Hsien-Wei Chen

Chi-Hsi Wu

Po-Hao Tsai

Wei-Cheng Wu

Ying-Ju Chen

Tsung-Shu Lin

Chin-Chuan Chang

Ming-Shih Yeh

Ming Shih Yeh

Ta-Wei Liu

In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Semiconductor packages

A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

Devices employing thermal and mechanical enhanced layers and methods of forming same

A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

Photonic integrated package and method forming same

A method for forming a chip package structure is provided. The method includes forming a first molding layer surrounding a first chip structure. The method includes disposing a second chip structure over the first chip structure and the first molding layer. The method includes forming a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The method includes forming a third molding layer surrounding the first molding layer and the second molding layer. The method includes disposing a third chip structure over the second chip structure, the second molding layer and the third molding layer. The method includes forming a fourth molding layer surrounding the third chip structure and over the second chip structure, the second molding layer, and the third molding layer.

Method for forming chip package structure with molding layer

A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

Chip package structure with bump

A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Package structure and manufacturing method thereof

A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Growing community of inventors

Taipei, Taiwan

Wei-yu Chen