International Business Machines Corporation

Wei-Yi Xiao

William J Lewis

Dean G Bair

Thomas Ruane

Chung-Lung K Shum

Christopher A Krygowski

Robert O Dryfoos

Shawfu Chen

Michael P Mullen

Allan Feldman

David Y Hu

Peter A Lewis

Masashi E Miyake

Vasantha R Vuyyuru

Dean G Blair

Robert J Adkins

A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state.

Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model

A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.

Method, system, and computer program product for out of order instruction address stride prefetch performance verification

A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.

Method, system and computer program product for register management in a simulation environment

A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first 'snap shot' of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another 'snap shot' of scan ring data is taken. The &#x201c;snap shots&#x201d; are compared and if both of the &#x201c;snap shots&#x201d; are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two &#x201c;snap shots,&#x201d; it becomes necessary to locate the broken spot within the large number of scan latches.

Multi-thread parallel segment scan simulation of chip element performance

A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first 'snap shot' of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another 'snap shot' of scan ring data is taken. The &#x201c;snap shots&#x201d; are compared and if both of the &#x201c;snap shots&#x201d; are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two &#x201c;snap shots,&#x201d; it becomes necessary to locate the broken spot within the large number of scan latches.

A method and apparatus for switching messages from a primary message channel to a secondary message channel in a message queuing system in which messages are placed in a first transmission queue of a local system for transmission to a remote system via a primary message channel. A local queue manager continuously checks to see whether a high water mark has been reached in the first transmission queue, indicating an apparent failure in the primary message channel. On determining such an apparent failure in the primary message channel, the queue manager determines whether the secondary message channel is associated with the first transmission queue. If so, the queue manager activates the secondary message channel to serve said first transmission queue. If, on the other hand, the secondary message channel is associated with another transmission queue, the queue manager transfers messages already in the first queue to the other queue and redirects any new messages intended for the first queue to the other queue. If the other transmission queue was previously empty, the secondary message channel is activated by a trigger to serve the other queue.

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Poughkeepsie, NY, United States of America

Wei-Yi Xiao