Hewlett-packard Development Company, L.P.

Hewlett Packard Enterprise Development LP

Wei Yi

Jianhua Yang

Gilberto Medeiros Ribeiro

John Paul Strachan

Feng Miao

Richard Stanley Williams

Matthew D Pickett

Frederick A Perner

Minxian Max Zhang

Muhammad Shakeel Qureshi

Shih-Yuan Wang

Zhiyong Li

Wei Guang Wu

Min Hu

Richard J Carter

Fung Suong Ou

Michael Josef Stuke

Julien Borghetti

Frekerick Perner

A memristor has a first electrode, a second electrode parallel to the first electrode, and a switching layer disposing between the first and second electrodes. The switching layer contains a conduction channel and a reservoir zone. The conduction channel has a Fermi glass material with a variable concentration of mobile ions. The reservoir zone is laterally disposed relative to the conduction channel, and functions as a source/sink of mobile ions for the conduction channel. In the switching operation, under the cooperative driving force of both electric field and thermal effects, the mobile ions are moved into or out of the laterally disposed reservoir zone to vary the concentration of the mobile ions in the conduction channel to change the conductivity of the Fermi glass material.

High-reliability high-speed memristor

A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.

Method and circuit for switching a memristive device

A memristor with a channel region in thermal equilibrium with a containing region. The channel region has a variable concentration of mobile ions. The containing region, formed of stoichiometric crystalline material, contains and is in thermal equilibrium with the channel region.

Memristor with channel region in thermal equilibrium with containing region

A heat mitigated bipolar resistive switch includes a BRS matrix sandwiched between first and second electrodes and a heat mitigator. The BRS matrix is to support bipolar switching of a conduction channel formed between the first and second electrodes through BRS matrix. The heat mitigator is to reduce heat in the BRS matrix generated during bipolar switching. The heat mitigator includes one or both of a parallel-connected NDR element to limit current flowing in the BRS matrix and a high thermal conductivity material to conduct the generated heat away from the BRS matrix above a predetermined elevated temperature.

Bipolar resistive switch heat mitigation

A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.

Method and circuit for switching a memristive device in an array

The present disclosure provides a data storage device that includes multi-level memory cells. The data storage device may include circuitry configured to write data to the multi-level memory cell. The write circuitry may include compliance circuitry configured to implement continuously tunable switching. The write circuitry may be configured to select a compliance mode for the switching, the compliance mode being selected from the group comprising current compliance and voltage compliance.

Multi-level memory cell with continuously tunable switching

An apparatus includes a substrate and a plurality of nano-fingers attached at respective first ends to the substrate and freely movable along their lengths, in which a first set of the plurality of nano-fingers comprises a first physical characteristic, wherein a second set of the plurality of nano-fingers comprises a second physical characteristic, and wherein the first physical characteristic differs from the second physical characteristic.

Apparatus having nano-fingers of different physical characteristics

On example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and a device layer. The device layer comprises a first dielectric material, between the first and second conductive electrodes, that includes an effective device layer, a first barrier layer near a first interface between the first conductive electrode and the device layer, and a second barrier layer near a second interface between the second conductive electrode and the device layer. A second example of the present invention is an integrated circuit that incorporates nanoscale electronic devices of the first example.

Nanoscale electronic device with barrier layers

In one example, an oxide-based negative differential resistance comparator circuit includes a composite NDR device that includes a first electrode, a first thin film oxide-based negative differential resistance (NDR) layer in contact with the first electrode and a central conductive portion. The composite NDR device also includes a second thin film oxide-based NDR layer disposed adjacent to the first NDR layer and a second electrode. A resistor may be placed in series with the composite NDR device and an electrical energy source can apply applying a voltage across the first electrode and second electrode. The composite NDR device produces a threshold based comparator functionality in the comparator circuit.

Negative differential resistance comparator circuits

A two-dimensional array of switching devices comprises a plurality of crossbar tiles. Each crossbar tile has a plurality of row wire segments intersecting a plurality of column wire segments, and a plurality of switching devices each formed at an intersection of a row wire segment and a column wire segment. The array has a plurality of lateral latches disposed in a plane of the switching devices. Each lateral latch is linked to a first wire segment of a first crossbar tile and a second wire segment of a second crossbar tile opposing the first wire segment. The lateral latch is operable to close or open to form or break an electric connection between the first and second wire segments.

Reconfigurable crossbar memory array

A node placement apparatus, system and method employ an optical source to define a grid for placement of nodes. The node placement apparatus includes a structure that provides a predetermined height and the optical source positioned at the predetermined height. The optical source is configured to produce an optical beam having a predetermined declination angle. The optical beam is configured to provide illumination of a plurality of discrete points on a surface to define the grid. The system further includes the nodes. The method of node placement includes locating the optical source above a fixed point on and at the predetermined height above the surface, illuminating the plurality of discrete points with the optical beam, and positioning a node at a selected discrete point of the plurality of discrete points illuminated by the optical beam.

Node placement apparatus, system and method

A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.

Memory array with write feedback

A memristor includes a first electrode of a nanoscale width; a second electrode of a nanoscale width; and an active region disposed between the first and second electrodes. The active region has a both a non-conducting portion and a source of dopants portion induced by electric field. The non-conducting portion comprises an electronically semiconducting or nominally insulating material and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field. The non-conducting portion is in contact with the first electrode and the source of dopants portion is in contact with the second electrode. The second electrode comprises a metal reservoir for the dopants. A crossbar array comprising a plurality of the nanoscale switching devices is also provided. A process for making at least one nanoscale switching device is further provided.

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Mountain View, CA, United States of America

Wei Yi