Micron Technology Incorporated

Intel Corporation

Lodestar Licensing Group LLC

Intel Corporatino

Wei Yeeng Ng

Andrew Li

Matthew J King

Yi Hu

Tom Jibu John

Xiaosong Zhang

Yiping Wang

Chandra S Tiwari

Yongjun Jeff Hu

Haoyu Li

James C Brighten

Kunal Shrotri

Andrew Bicksler

Daniel Billingsley

Ramey M Abdelrahaman

Lance Williamson

Frank Speetjens

Narula Bilik

Rajesh Balachandran

Sukhdeep Kaur

Sangeetha P Komanduri

Zhenyu Bo

Joan M Kash

David Neumeyer

Yung K Pak

Jun Liu

Gordon A Haller

Adam William Saxler

John Mark Meldrim

Hongbin Zhu

Anish A Khandekar

Fei Wang

Christopher W Petz

Joseph Neil Greeley

Erik R Byers

Diem Thy N Tran

Prakash Rau Mokhna Rau

Ian C Laboriante

Nicholas R Tapias

Jun Zhao

Saurabh Keshav

Wesley O McKinsey

Jeremy F Adams

Chandra Tiwari

Mark A Levan

Zhiqiang Xie

Ho Yee Hui

Philip M Campbell

A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

Systems and methods for mitigating crack propagation in semiconductor die manufacturing

A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

Microelectronic devices including oxide material between decks thereof, and related memory devices

Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 10atoms/cmto about 10atoms/cm. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Microelectronic devices including an oxide material between adjacent decks

Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rwhich is the mean peak-to-valley distance along the undulating topography. The Ris at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having rugged material fill, and methods of forming integrated assemblies

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

Microelectronic devices including an oxide material between adjacent decks, electronic systems, and related methods

Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

Solid state memory device, and manufacturing method thereof

Growing community of inventors

Boise, ID, United States of America

Wei Yeeng Ng