Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

TSMC Nanjing Company, Limited

Wei-Yang Jiang

He-Zhou Wan

Xiu-Li Yang

Lu-Ping Kong

Kuan Cheng

Ching-Wei Wu

Cheng-Hung Lee

A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.

Static random access memory with adaptive precharge signal generated in response to tracking operation

A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.

Write circuit of memory device and method of operating the same

A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.

A device includes memory banks, a first pair of write data wirings, a second pair of write data wirings and a global write circuit. The first pair of write data wirings is connected to a first group among the memory banks. The second pair of write data wirings is connected to a second group among the memory banks. In response to a first clock signal, the global write circuit generates a first global write signal and a first complement global write signal transmitted to the first group among the memory banks through the first pair of write data wirings. In response to a second clock signal, the global write circuit generates a second global write signal and a second complement global write signal transmitted to the second group among the memory banks through the second pair of write data wirings.

Write circuit of memory device

A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages.

Growing community of inventors

Zhejiang, China

Wei-Yang Jiang