Yangtze Memory Technologies Co., Ltd.

Huazhong University of Science and Technology

Wuhan Lewei E-Commerce Co., Ltd

Huawei Technologies Co., Limited

Wuhan Lewei Electronic Commerce Co., Ltd.

Wuhan Wanshi Outdoor Co., Ltd.

Other

Wuhan Yadu Clothing Co., Ltd

Wei Xu

Pan Huang

Wenbin Zhou

Zongliang Huo

Ping Yan

Wenxiang Xu

Ji Xia

Haohao Yang

ZongLiang Huo

Yi Liu

Qingqing Wang

Beihan Wang

Bo Xu

Hongbin Zhu

Lei Xue

Juan Tang

Jianqiao Zou

Dinghao Dong

Yirong Tang

Song Yang

Zhipeng Wu

Bin Yuan

Xiangning Wang

Zongke Xu

Lei Li

Zhen Guo

Yaping Zhang

Bin Chen

Yali Guo

Wenlong Li

Xiaofen Zheng

Han Ding

ChangKang Tang

Xiang Li

Simin Liu

Qian Yu

Jie Su

Jian Ge

Fei Xiong

Cheng Jiang

Xiaolei Liu

Bing Jia

Huichao Liu

Beibei Li

Kaiju Liao

Mingya Du

Qinggu Pan

Shijun Luo

Delong Hu

Fancong Zeng

Weiteng Liu

Jiwei Zhu

Zhengliang Xia

Meiyong Yu

Jingyue Su

Jinli Xu

Clare Conran

Francois Pitié

Fengyun Huang

Longxiang Yan

Fazhan Wang

Chunxiao Chen

Siliu Zhang

Yuan Yuan

Jinxing Chen

Qizhe Wang

Qiangqiang Niu

Guanglong Fan

Sheng Fen

Fuquan Jin

Three-dimensional NAND memory device and method that eliminate leakage currents and short circuits are provided. The method includes: forming a gate line slit through a plurality of alternating layers of an oxide layer and a conductive material layer, where the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and/or a portion of the sidewall of the gate line slit; and performing an etch process in the gate line slit to remove the conductive material layer that is weakened by the ion implantation process.

Three-dimensional NAND memory device and method that eliminate leakage currents and short circuits

The present disclosure discloses a three-dimensional memory and a fabrication method thereof. The fabrication method comprises: forming a stack structure comprising alternately stacked dielectric layers and sacrificial layers; forming a gate line slit penetrating vertically penetrating the stack structure and extending in a first horizontal direction; and etching portions of the dielectric layers and the sacrificial layers adjacent to the gate line slit to form a plurality of recesses, wherein an aperture of each recess in a vertical direction is greater than a thickness of a corresponding sacrificial layer.

Three-dimensional memory and fabrication method thereof

A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

Gateline mask design for removing sacrificial gateline polysilicon within stair step area

A method includes forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a trench through the stack to uncover the substrate to expose lateral sides of the insulating layers and the sacrificial layers, the trench extending from a core area to a stair step area of the stack; forming a liner to cover the exposed lateral sides; removing the liner in the trenches within a first area of the core area and the stair step area to expose the lateral sides of the sacrificial layers of the stack within the first area; removing the sacrificial layers within the first area; removing the liner in the trenches within a second area of the core area and the stair step area to expose the lateral sides of the sacrificial layers of the stack within the second area; and removing the sacrificial layers within the second area.

Method for removing sacrificial layers of a stack of a three-dimensional semiconductor structure in two steps

A method for forming a 3D memory device is disclosed. The method includes forming an alternating dielectric stack on a substrate. Then a plurality of channel structures and dummy channel structures vertically penetrating the alternating dielectric stack are formed, The channel structures are located in a core region, and the dummy channel structures are located in a staircase region. A gate line silt structure is formed vertically penetrating the alternating dielectric stack and laterally extending in a first direction. The gate line silt structure includes a narrow portion that has a reduced width along a second direction different from the first direction.

Three-dimensional memory devices and fabricating methods thereof

Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the method for forming the 3D memory device includes forming an alternating dielectric stack on a substrate, and forming channel holes that penetrate the alternating dielectric stack and expose at least a portion of the substrate. The method further includes forming top select gate openings that penetrate vertically an upper portion of the alternating dielectric stack and extend laterally. The method also includes forming slit openings parallel to the top select gate openings, wherein the slit openings penetrate vertically the alternating dielectric stack. The method also includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers, forming top select gate cuts in the top select gate openings, and forming slit structures in the slit openings.

Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a structure strengthen plug in an upper portion of the alternating dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a gate line silt in the alternating dielectric stack to expose a sidewall of one enlarged connecting portion of the structure strengthen plug; and forming a gate line slit structure in the gate line slit including an enlarged end portion connected to the one enlarged connecting portion of the structure strengthen plug.

Aspects of the disclosure provide a semiconductor device. The semiconductor device can include a trench formed in a first dielectric layer, a trench filler layer that fills a portion of the trench, a conductive layer over the trench filler layer, and a second dielectric layer over the conductive layer. The second dielectric layer is disposed in the trench. The semiconductor device can also include a contact structure configured to connect to the conductive layer through a hole in the second dielectric layer.

Contact structure and method of forming the same

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure including a memory block including a plurality of memory cells. The 3D memory device also includes a first top select structure and a bottom select structure in the memory block and aligned with each other vertically; and a second top select structure in the memory block is separated from the first top select structure by at least one of the plurality of memory cells. The first top select structure, the bottom select structure, and the second top select structure each includes an insulating material.

Three-dimensional memory device without gate line slits and method for forming the same

Pet sofa

Card box

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. First, a slit structure and a support structure are formed in a stack structure having interleaved a plurality of sacrificial material layers and a plurality of insulating material layers, the initial support structure between adjacent slit openings of the slit structure. A source structure is formed to include a source portion in each of the slit openings. A pair of first portions of a connection layer is formed in contact with and conductively connected to the source portion. A second portion of the connection layer is formed in contact with and conductively to the pair of first portions of the connection layer.

Three-dimensional memory device with source structure and methods for forming the same

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a first source contact portion in a substrate, forming a dielectric stack over the first source contact portion, and forming a slit opening extending in the dielectric stack and exposing the first source contact portion. The method also includes forming a plurality of conductor layers through the slit opening and form a second source contact portion in the slit opening and in contact with the first source contact portion.

Contact structures having conductive portions in substrate in three-dimensional memory devices and methods for forming the same

Pet bed

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers, a plurality of channel structures extending in the memory stack, and a source structure extending in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. Two adjacent source contacts are conductively connected to one another by a connection layer, the connection layer includes a pair of first portions being over the two adjacent ones of the plurality of source contacts and a second portion between the pair of first portions. A support structure is between the two adjacent source contacts. The support structure includes a cut structure over interleaved a plurality of conductor portions and a plurality of insulating portions.

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Wuhan, China

Wei Xu