Ceremorphic, Inc.

Samsung Display Co., Ltd.

Apple Inc.

Samsung Dispaly Co., Ltd.

Google Inc.

Wei Xiong

Ryan P Boesch

Martin Kraemer

Frank C Seto

Wei Hsin Yao

Hyunwoo Nho

Jie Won Ryu

Sun-il Chang

Venkat Mattela

Hyunsoo Kim

Robert F Wiser

Patrick R Cruce

Xia Li

Hopil Bae

Amir Amirkhany

Derek Keith Shaeffer

Kingsuk Brahma

Mahesh B Chappalli

Chen Chen

Henry C Jen

Hao-Lin Chiu

Sanquan Song

Kwang Soon Park

Xiang Lu

Dale F Stolitzka

David Morris Hoffman

Majid Gharghi

Yael Pritch Knaan

Stanley B Wang

Tianfan Xue

Yao Shi

Nikhil Acharya

Sunmin Jang

Orly Liba

Pablo Moreno Galbis

Hari P Paudel

Kfir Aberman

Feng Yu

Yongjie Jiang

Ionut A Mirel

Dongwon Kwon

Shengzhe Jiao

Haojiang Zhou

Ling Zhang

Ruicong Chen

Nicolas Le Dortz

Jialin Liu

Arjunsimha Chaturbhuj

Ruofan Zhang

David Futschik

Daniel Sykora

An analog machine learning architecture uses modular analog multiplier-accumulator (AMAC) elements of fixed size to form a machine learning (ML) system with increasing feature map size. A single 3×3×64 AMAC array is arranged to provide a three layer ML architecture with first layer 3×3×64, second layer 3×3×128, and third layer 3×3×256 using arrangements of single 3×3×64 AMACs arranged in parallel, where the bias of each AMAC is separately established in a unique interval of time.

Modular analog multiplier-accumulator unit element for multi-layer neural networks

A display system may include a plurality of light emitting diodes to emit light, where each of the light emitting diodes are connected in parallel and a plurality of first switches respectively coupled to the plurality of light emitting diodes. A first switch of the plurality of first switches is coupled in parallel to a first light emitting diode. The first switch may short the first light emitting diode of the plurality of light emitting diodes through a defined resistor having a defined value that therefore draws a defined short circuit current.

Systems and methods for mitigating micro-LED failures

A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values, and a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. The X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

Analog multiplier accumulator with unit element gain balancing

Embodiments herein provide various apparatuses and techniques to efficiently mitigate front-of-screen (FoS) artifacts that may occur due to voltage fluctuations due to alternating current (AC) or direct current (DC) mechanisms that may occur in a variety of pixel types. In one embodiment, emission profile awareness circuitry may be implemented to mitigate for FoS artifacts due to DC mechanisms. Two-dimensional (2D) digital compensation circuitry may address the DC portion of the voltage fluctuations by accounting for an emission profile applied to content displayed on an electronic display. In some embodiments, the 2D digital compensation circuitry may compensate for the AC portion of the voltage fluctuations by duplicating the AC voltage fluctuations via voltage error subtraction circuitry and voltage error accumulation circuitry.

Feedforward compensation of high-luminance banding Mura compensation

An electronic device may include an electronic display having a gate-on-array (GOA) that generates gate signals in response to an activation signal, pixels that activate in response to a combination of the gate signals and data signals indicative of image data, and sensing circuitry. The sensing circuitry may measure a characteristic response of a gate signal a characteristic response of one or more pixels, or both and compare the characteristic responses to baselines. The electronic device may also include compensation circuitry that applies a compensation to the activation signal and/or to the image data based on the comparisons between the characteristic responses and the baselines.

Display panel transistor gate-signal compensation systems and methods

A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.

Bias unit element with binary weighted charge transfer lines

An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

Chopper stabilized analog multiplier accumulator with binary weighted charge transfer capacitors

A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.

Differential unit element for multiply-accumulate operations on a shared charge transfer bus

A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.

Multiplier-accumulator unit element with binary weighted charge transfer capacitors

A plurality of unit elements share a charge transfer bus, each unit element accepts A and B digital inputs and generates a product P as an analog charge transferred to the charge transfer bus, each unit element comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates of each unit element are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges contributed by all unit elements to the charge transfer lines according to a bit weight and converted to a digital value output.

Scaleable analog multiplier-accumulator with shared result bus

A differential multiplier-accumulator accepts A and B digital inputs plus a sign bit and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. One of the positive and negative unit element is enabled by the sign bit, the enabled unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element, which charge to charge transfer lines, and the charge transfer lines are coupled to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product.

Differential analog multiplier for a signed binary input

A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.

Differential analog multiplier-accumulator

A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

Unit element for asynchronous analog multiplier accumulator

Cascade multiplier using unit element analog multiplier-accumulator

An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

Architecture for analog multiplier-accumulator with binary weighted charge transfer capacitors

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Wei Xiong