Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Wei-Xiang You

Szuya Liao

Cheng-Yin Wang

Chenming Hu

Pin Chia Su

Kai-Shin Li

A semiconductor device includes a first memory cell and a second memory cell. The first memory cell is configured to store a first data bit at a first node when the first memory cell is turned on. The second memory cell is configured to store the first data bit when the first memory cell is turned off. The first memory cell comprises a first switch coupled to the first node, and the first switch is configured to transmit the first data bit to the second memory cell, and configured to be turned off when the first memory cell is turned off.

Semiconductor device and operating method thereof

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

Static random-access memory (SRAM) device and related SRAM-based compute-in-memory devices

A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

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Kaohsiung, Taiwan

Wei-Xiang You