Intel Corporation

Wei Wu

Shih-Lien L Lu

Shigeki Tomishima

Jawad Basit Khan

Charles Augustine

Christopher J Hughes

Dinesh Somasekhar

James W Tschanz

Sanjeev Kumar

Rajesh Sundaram

Alaa R Alameldeen

Chetan Chauhan

David Champagne

Abhishek Tiwari

Rajat Agarwal

Zeshan A Chishti

Jiangtao Li

Patrick Koeberl

Helia A Naeimi

Yi Zou

David M Durham

Muhammad M Khellah

Sanjeev N Trika

Christopher B Wilkerson

Karanvir S Grewal

Xin Guo

Sergej Deutsch

Srikanth T Srinivasan

Brian J Hickmann

Vivek Joy Kozhikkottu

Kjersten E Criss

Georgios Panagopoulos

Kuljit Singh Bains

Siddhartha Chhabra

Sanu K Mathew

Wei P Chen

Carlos V Rozas

Francis X Mckeen

John B Halbert

Thomas D Fletcher

Vallabhajosyula S Somayazulu

Gregory Kengho Chen

Omesh Tickoo

Bin Xing

Krystof C Zmudzinski

Dennis Ryan Bradford

Sorin Iacobovici

Theodros Yigzaw

David Johnston

Zhe Wang

Jing Ling

Carlos Alfonso Tokunaga

Vered Bar Bracha

Deep K Buch

John G Holm

Somnath Paul

Roger Espasa

Andrew M Rudoff

Sreenivas Mandava

Mark Shanahan

Chris Wilkerson

Henry Stracovsky

Sourabh Dongaonkar

Gregory M Iovino

Kevin Gotze

Uksong Kang

Yi Li

Guillem Sole

Tal Azogui

Shankar Ganesh Ramasubramanian

James J Greensky

Byoungchan Oh

Amir Ali Radjai

Melin Dadual

Hussein Alameer

Hsing-Min Chen

Kon-Woo Kwon

Ilya Wagner

Shih-Lien L Liu

Ed Prack

Jason Van Dyken

Aditya Nagaraja

Joshua Underdown

Vaibhav Singh

Jon Stephan

Aravinda K Radhakrishnan

Shih Lien L Lu

Vivek Kozhikkottu

A near memory compute system includes multiple computation nodes, such as nodes for parallel distributed processing. The nodes include a memory device to store data and compute hardware to perform a computation on the data. Error correction code (ECC) logic performs ECC on the data prior to computation on the data by the compute hardware. The node also includes residue check logic to perform a residue check on a result of the computation.

End-to-end data protection for compute in memory (CIM)/compute near memory (CNM)

Methods and apparatus for sparse column-aware encodings for numeric data types, including integer data and floating-point data (float, double, etc.). The encoding schemes are tailored to take advantage of column addressable memories such as stochastic associative memories (SAM) to enable Stochastic Associative Search (SAS), which is a highly efficient and fast way of searching through a very large database of records (order of Billions) and finding similar records to a given query record (search key). Techniques are also disclosed for performing range searches for both integer and floating-point data types. The integer or float data is converted to Hexadecimal form and encoded using an m-of-n constant weight encoding. Only the columns with set bits in search keys need to be read, which significantly reduces the number of reads required for searches.

Sparse column-aware encodings for numeric data types

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

An embodiment of an electronic apparatus may include a substrate, and logic coupled to the substrate, the logic to determine a base value to compress a block of data, wherein the block of data consists of a first number of data words, replace original values from a second number of data words from the block of data with respective delta values from the base value to provide compressed data, wherein the second number of data words is at least two less than the first number of data words, and store metadata associated with the block of data together with the compressed data in the block of data. Other embodiments are disclosed and claimed.

Low-complexity coverage-based compression

Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

Technologies for preserving error correction capability in compute-in-memory operations

Technologies for performing encoding of data symbols for column read operations include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to obtain a data set to encode. The data set is defined by a set of data symbols. The circuitry is also configured to determine a set of codewords to encode the data symbols of the data set, including defining each codeword with a set bit distance of at least two from every other codeword in the set of codewords. Additionally, the circuitry is configured to write the data set to the memory as a function of the determined set of codewords.

Technologies for performing encoding of data symbols for column read operations

Technologies for provisioning error-corrected data for use in in-memory compute operations include a memory that includes a memory media having multiple memory partitions and media access circuitry coupled to the memory media. The media access circuitry is to receive a request to perform an in-memory compute operation on data from the memory media. The request specifies a memory partition of the memory media in which the data is located. The media access circuitry reads the data from the memory partition. The media access circuitry performs error correction on the read data to produce error-corrected read data and stores the error-corrected read data in a temporary buffer for access by one or more in-memory compute operations, in addition to the requested in-memory compute operation.

Technologies for providing ECC pre-provisioning and handling for cross-point memory and compute operations

Examples include techniques to improve implement an error correction codeword (ECC) scheme to protect data stored to a memory from both hard and random bit errors using a hybrid ECC scheme that includes generation of first and second codewords to protect the data.

Techniques to implement a hybrid error correction code scheme

An apparatus is described. The apparatus includes memory controller logic circuitry to interface to a multi-level memory having a higher memory level to act as a memory side cache for a lower memory level. The memory controller logic circuitry having policy determination circuitry to prevent lesser accessed data items from occupying space in the higher memory level at the expense of more frequently accessed data items.

Caching bypass mechanism for a multi-level memory

Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.

Technologies for providing multiple levels of error correction

Provided are an apparatus, memory device, and method to determine error location polynomial coefficients to provide to bit correction logic instances to decode bits of a codeword. A memory controller for a memory includes coefficient generating logic to receive as input a plurality of syndrome values to generate a plurality of coefficients for an error locator polynomial. A plurality of instances of bit correction logic, one instance for each bit of bits to correct in a codeword for a block in the memory array to decode. Each instance of bit correction logic is to receive as input the coefficients for the error locator polynomial and elements for the bit to correct from a decoder alphabet to determine whether to correct the bit and output as a decoded bit the bit or a corrected bit to include in a decoded codeword.

Error correction of multiple bit errors per codeword

An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.

Fast search of error correction code (ECC) protected data in a memory

Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.

Minimal aliasing bit-error correction code

In one embodiment, an apparatus comprises a controller comprising circuitry, the controller to generate an error correction code for a memory line, the memory line comprising a plurality of first data blocks, wherein the error correction code comprises parity bits generated based on first portions of a plurality of second data blocks, wherein the plurality of second data blocks are the first data blocks or diffused data blocks generated from the plurality of first data blocks; generate a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least one metadata bit; encode the first data blocks and the metadata block; and provide the encoded data blocks and the encoded metadata block for storage on a memory module.

System for identifying and correcting data errors

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Portland, OR, United States of America

Wei Wu