The State University of New York

General Electric Company

Wei Wang

David Scott Diwinsky

Arpit Jain

Xiao Bian

Bernard Patrick Bewlay

Peijun Ding

William A Lanford

Longyin Wen

Ser Nam Lim

Swaminathan Sankaranarayanan

Robert E Geer

Tong Jing

A system includes a borescope and at least one processor. The borescope includes a camera configured to acquire an acquisition series of frames of at least one target component. The at least one processor is operably coupled to the camera, and is configured to acquire the acquisition series of frames from the camera; determine a blurriness metric value for each of the frames; select frames that satisfy a threshold for the blurriness metric value to form an inspection series of frames; and perform an inspection analysis for the at least one target component using the inspection series of frames.

Systems and methods for improved component inspection

A system includes one or more processors configured to detect perimeter edges of one or more rotor blades of a turbine assembly as depicted in a series of image frames using boundary analysis performed on the image frames. The one or more processors are configured to identify a set of the image frames as key frames based on positional offsets between the perimeter edges that are detected in the image frames and a reference blade pose such that the key frames are able to be inspected for objects-of-interest without inspecting the image frames that are not the key frames.

System and method for image-based target object inspection

A system includes one or more processors configured to analyze obtained image data representing a rotor blade to detect a candidate feature on the rotor blade and determine changes in the size or position of the candidate feature over time. The one or more processors are configured to identify the candidate feature on the rotor blade as a defect feature responsive to the changes in the candidate feature being the same or similar to a predicted progression of the defect feature over time. The predicted progression of the defect feature is determined according to an action-guidance function generated by an artificial neural network via a machine learning algorithm. Responsive to identifying the candidate feature on the rotor blade as the defect feature, the one or more processors are configured to automatically schedule maintenance for the rotor blade, alert an operator, or stop movement of the rotor blade.

Neural network feature recognition system

Reconfigurable 3D interconnect is provided that can be used for digital and RF signals. The reconfigurable 3D interconnect can include an array of vertical interconnect vias (or TSVs) providing a signal path between a first core element of a 3D IC and a second core element of the 3D IC stacked above the first core element. A routing circuit can be used to route a signal from the first core element to the second core element through selected TSVs of the array of TSVs providing the signal path between the first core element and the second core element. The routing circuit allows re-routing of the signal through different selected TSVs during operation, which can provide real time adjustments and capacity optimization of the TSVs passing the particular signal between the elements.

Reconfigurable RF/digital hybrid 3D interconnect

A hybrid CMOL stack enables more efficient design of CMOS logical circuits. The hybrid CMOL structure includes a first substrate having a CMOS device layer on the substrate, a first interconnect layer with interface pins over the CMOS device layer of the first substrate, a first array of nanowires connected to the interface pins of the first interconnect layer, a layer of nanowire junction material over the first array of nanowires, a second array of nanowires over the nanowire junction material, a second interconnect layer having interface pins disposed over the second array of nanowires, the interface pins being connected to the second array of nanowires, and a second substrate, the second substrate including a second CMOS device layer disposed over the second interconnect layer.

Three-dimensional architecture for integration of CMOS circuits and nano-material in hybrid digital circuits

A copper conductor is formed which is included as a component in microelectronic devices. The conductor is formed by forming a metal layer on the surface of a microelectronic substrate, forming a copper layer on the metal layer, and annealing the metal and copper layers. The annealing step diffuses at least some of the metal layer through the copper layer to the surface thereof where the diffused metal forms a protective metal oxide at the surface of the copper layer. As a result, the metal oxide layer passivates the copper layer.

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Niskayuna, NY, United States of America

Wei Wang