International Business Machines Corporation

Globalfoundries Inc.

Wei Wang

Chih-Chao Yang

Lawrence Alfred Clevenger

Terry Allen Spooner

Roger Allan Quon

Injo Ok

Balasubramanian Pranatharthiharan

Philip Shi-lung Yu

Jiong Yang

Kevin W Brew

Kangguo Cheng

Zheng Xu

Zhenxing Bi

Su Chen Fan

Koichi Motoyama

Huai Huang

Hosadurga K Shobha

Alexander Reznicek

Ruilong Xie

Theodorus E Standaert

Cedric Lichtenau

Vijayalakshmi Srinivasan

Kailash Gopalakrishnan

David Brian Mitzi

Lan Yu

Tao Li

Swagath Venkataramani

Tsung-Sheng Kang

Youngseok Kim

Yulong Li

Sunil K Shukla

Marinus Hopstaken

Razvan Peter Figuli

Mark T Winkler

Holger Horbach

Martin A Lutz

Chi-Chao Yang

Processing input data for transmittal to a data consumer such as an artificial intelligence engine is performed by arranging the input data into a uniform structure made up of sticks of data combined to form pages of sticks. A stick is any well-sized set of input data elements whereby the size of the stick is fixed. A masking pattern is established for sticks of data having certain ranges of invalid data for consumption of partial sticks while maintaining validity of the input data being transferred. The mask pattern is derived based on set-active-mask-and-value (SAMV) instructions. The derived mask pattern is carried forward for subsequent load instructions to the data consumer.

Padding input data for artificial intelligence accelerators

A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.

Phase change memory using multiple phase change layers and multiple heat conductors

An integrated circuit, a system, and a method to integrate phase change memory and magnetoresistive random access memory within a same integrated circuit in a system. The integrated circuit may include an MRAM and a PCM. The MRAM may include an MRAM bottom electrode, an MRAM stack, and an MRAM top electrode. The PCM may include a PCM bottom electrode, where the PCM bottom electrode has a lower height than the MRAM bottom electrode, a phase change material, and a PCM top electrode.

AI accelerator with MRAM, PCM, and recessed PCM bottom electrode

An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.

Mixed conducting volatile memory element for accelerated writing of nonvolatile memristive device

A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.

Confined phase change memory with double air gap

A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein.

Tunable on-chip nanosheet resistor

A method is presented for constructing a three-dimensional (3D) stack phase change memory (PCM) device. The method includes forming a plurality of stack layers over a plurality of conductive lines, the plurality of conductive lines formed within trenches of an inter-layer dielectric (ILD), forming isolation trenches extending through the plurality of stack layers, etching the plurality of stack layers to define an opening, filling the opening with at least a phase change material, and constructing vias to the plurality of conductive lines.

3D phase change memory

A semiconductor device includes a first type nanosheet device having a first plurality of nanosheet portions alternately stacked with a first plurality of work function metal layers on a substrate, and a second type nanosheet device having a second plurality of nanosheet portions alternately stacked with a second plurality of work function metal layers on the substrate. The second type nanosheet device is spaced apart from the first type nanosheet device. The semiconductor device also includes a dielectric layer disposed in the space between the first and second type nanosheet devices. The first and second plurality of work function metal layers are directly disposed on the dielectric layer, and bottom surfaces of the directly disposed first and second plurality of work function metal layers are co-planar with each other.

Patterning method for nanosheet transistors

A conductive interface includes a first conductor having a recessed area in least one surface. A dielectric layer has a trench positioned over the first conductor. A nitridized layer is formed on a top surface of the first conductor around the recessed area, to a depth on the first conductor that is shallower than a depth of the recessed area. A second conductor is formed in the trench and the recessed area to form a conductive contact with the first conductor.

Surface nitridation in metal interconnects

A multipurpose semiconductor process chamber includes a vessel wall that encloses contiguous first and second volumes of the multipurpose chamber, and means for selectively effectively preventing ions moving across a plane that partitions the first volume from the second volume. For example, the means can include an electromagnet, or at least one permanent magnet, that is operable to impose and remove a magnetic field with field lines extending in the plane.

Selective ion filtering in a multipurpose chamber

Methods of forming vias include nitridizing exposed surfaces of a first layer and an exposed surface of a conductor underlying the first layer to form a layer of nitridation at said exposed surfaces. Material from the layer of nitridation at the exposed surface of the underlying conductor is etched away. The exposed surface of the underlying conductor is etched away to form a recessed area in the underlying conductor after etching away material from the layer of nitridation. A conductive via that forms a conductive contact with the underlying conductor is formed.

A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.

Nitridization for semiconductor structures

Growing community of inventors

Yorktown Heights, NY, United States of America

Wei Wang