Kymab Limited

Arm Limited

University of Michigan

The University of Southampton

Wei Wang

E-Chiang Lee

Allan Bradley

Qi Liang

Jasper Clube

Hui Liu

Dominik Spensberger

Stephan Diestelhorst

Glenn A Friedrich

Wendy Arnott Elsasser

John Kenneth Blackwood

Roberto Magliozzi

Peter Chen

Parameshwarappa Anand Kumar Savanth

Prakash Shyamlal Ramrakhyani

Thomas Friedrich Wenisch

Satish Narayanasamy

Matthew James Walker

Vaibhav Gogte

Shidhartha Das

James Edward Myers

Mbou Eyole

Andreas Lars Sandberg

Matthew James Horsnell

Ian Kirby

Balaji Venu

Supreet Jeloka

Giacomo Gabrielli

Nikos Nikoleris

Andreas Hansson

Gustavo Federico Petri

Irenéus Johannes De Jong

Alexander Stewart Weddell

Andrew Wood

Thomas Edward Shull

Jiajun Wang

Anais Legent

Emily Kathryn Ruppel

Peter M Chen

A method and apparatus generate computer executable code as one or more code portions, detect a number of processing operations required to reach one or more predetermined stages in execution of each code portion, and associate with each code portion one or more progress indicators, each representing a respective execution stage of the one or more predetermined stages within execution of that code portion. Further aspects include, when a current execution stage of the program code is at least at the execution stage represented by the progress indicator, a first operation may be performed, and when the current execution stage of the program code is before the execution stage represented by the progress indicator, a second operation different from the first operation is performed.

Method and apparatus for instruction checkpointing in a data processing device powered by an unpredictable power source

An apparatus has processing circuitry with support for transactional memory, and a cache hierarchy comprising at least two levels of cache. In response to a draining trigger event having potential to cause loss of state stored in at least one further level cache beyond a predetermined level cache in which speculative store data generated by a transaction is marked as speculative until the transaction is committed, draining circuitry performs a draining operation to scan a subset of the cache hierarchy to identify dirty cache lines and write data associated with the dirty cache lines to persistent memory. The subset of the cache hierarchy includes the at least one further level cache. In the draining operation, speculative store data marked as speculative in the predetermined level cache is prevented from being drained to the persistent memory.

Draining operation for draining dirty cache lines to persistent memory

A data processing apparatus includes obtain circuitry that obtains a stream of instructions. The stream of instructions includes a barrier creation instruction and a barrier inhibition instruction. Track circuitry orders sending each instruction in the stream of instructions to processing circuitry based on one or more dependencies. The track circuitry is responsive to the barrier creation instruction to cause the one or more dependencies to include one or more barrier dependencies in which pre-barrier instructions, occurring before the barrier creation instruction in the stream, are sent before post-barrier instructions, occurring after the barrier creation instruction in the stream, are sent. The track circuitry is also responsive to the barrier inhibition instruction to relax the barrier dependencies to permit post-inhibition instructions, occurring after the barrier inhibition instruction in the stream, to be sent before the pre-barrier instructions.

Instruction ordering

Bispecific antigen binding molecules (e.g., antibodies) that bind blood clotting factors, factor IXa (FIXa) and factor X (FX), and enhance the FIXa-catalysed activation of FX to FXa. Use of the bispecific antigen binding molecules to control bleeding, by replacing natural cofactor FVIIIa which is deficient in patients with haemophilia A.

FIXaxFX bispecific antibody with common light chain

An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

Issuing a sequence of instructions including a condition-dependent instruction

Bispecific antibodies for factor IX and factor X

The invention discloses methods for the generation of chimaeric human&#x2014;non-human antibodies and chimaeric antibody chains, antibodies and antibody chains so produced, and derivatives thereof including fully humanised antibodies; compositions comprising said antibodies, antibody chains and derivatives, as well as cells, non-human mammals and vectors, suitable for use in said methods.

Animal models and therapeutic molecules

In a particular implementation, a method includes: receiving, at a computing device, first and second instructions of a plurality of instructions obtained from a memory, where the first instruction corresponds to a preceding instruction of a second instruction, and where the second instruction corresponds to a succeeding instruction of the first instruction; determining a dependency of the first and second instructions; sending the first and second instructions to an issue queue of the computing device; executing, at the computing device, the first and second instructions; and completing, at the computing device, the first and second instructions.

Systems and methods for defining a dependency of preceding and succeeding instructions

The invention discloses methods for the generation of chimaeric human-non-human antibodies and chimaeric antibody chains, antibodies and antibody chains so produced, and derivatives thereof including fully humanised antibodies; compositions comprising said antibodies, antibody chains and derivatives, as well as cells, non-human mammals and vectors, suitable for use in said methods.

An apparatus comprises a write buffer to buffer store requests issued by the processing circuitry, prior to the store data being written to at least one cache. Draining circuitry detects a draining trigger event having potential to cause loss of state stored in the at least one cache. In response to the draining trigger event, the draining circuitry performs a draining operation to identify whether the write buffer buffers any committed store requests requiring persistence, and when the write buffer buffers at least one committed store request requiring persistence, to cause the store data associated with the at least one committed store request to be written to persistent memory. This helps to eliminate barrier instructions from software, simplifying persistent programming and improving performance.

Draining operation to cause store data to be written to persistent memory

Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.

Hardware bit-vector techniques

The invention discloses methods for the generation of chimaeric human&#x2014;non-human antibodies and chimaeric antibody chains, antibodies and antibody chains so produced, and derivatives thereof including fully humanised antibodies; compositions comprising the antibodies, antibody chains and derivatives, as well as cells, non-human mammals and vectors, suitable for use in the methods.

Various implementations described herein are directed to an integrated circuit having a cache with memory components that store data with multiple addresses. The integrated circuit may include a controller that communicates with the cache to provide directives to the cache. The integrated circuit may include a refresh circuit that interprets the directives received from the controller to generate interpretation information based on determining one or more particular addresses of the multiple addresses that no longer need refreshing. The refresh circuit may further employ the interpretation information to skip the need for refreshing the one or more particular addresses pointing to the memory components in the cache that no longer need refreshing.

Refresh circuit for use with integrated circuits

Disclosed are devices, method and/or systems for responding to a request for accessing a portion of a memory prior to completion of a requested operation to place the portion of the memory in an initialized state. In one example implementation, a memory controller may delay initiation of a write operation addressed to a particular portion of the memory until completion of a pending request to initialize the particular portion of the memory. In another example implementation, a memory controller may return values to service a request for a read operation comprising values representing an initialized state without accessing the particular portion of the memory responsive to a presence of a pending request to initialize the particular portion of the memory.

Initialisation of a storage device

Growing community of inventors

Cambridge, United Kingdom

Wei Wang