International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Wei-Tsu Tseng

Shyng-Tsong Chen

Adam D Ticknor

John H Zhang

Andrew Herbert Simon

Laertis Economikos

Mahadevaiyer Krishnan

David Lee Rath

Kaushik Arun Kumar

Daniel C Edelstein

Timothy Joseph Dalton

Hariklia Deligianni

Katherine Lynn Saenger

Sandra Guy Malhotra

John Michael Cotte

Thomas W Dyer

Chandrasekhar Narayan

Panayotis Constantinou Andricacos

Michael F Lofaro

Chao-Kun Hu

Christy Sensenich Tyberg

Lee Matthew Nicholson

James Aloysius Hagan

Judith Marie Rubino

Jim Shih-Chun Liang

Kenneth M Davis

Fen Fen Jamin

Domingo A Ferrer

Steffen K Kaldor

Sean P E Smith

Tze-man Ko

Ben Kim

Robin Van Den Nieuwenhuizen

Manoj Balachandran

Deoram Persaud

Shom Ponoth

Qinghuang Lin

Terry Allen Spooner

George Stojan Tulevski

Jiehui Shu

Stephen Edward Greco

Kathryn Turner Schonenberg

Mahmoud M Khojasteh

Shafaat Ahmed

Zhiguo Sun

Joyeeta Nag

Philippe M Vereecken

Qiang Fang

Dinesh R Koli

Philippe Mark Vereecken

Shahrukh Akbar Khan

Arthur W Martin

James J Steffes

Vamsi Devarapalli

Colin J Goyette

Michael R Kennett

The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

Cobalt plated via integration scheme

The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Dual medium filter for ion and particle filtering during semiconductor processing

The present disclosure relates to semiconductor structures and, more particularly, to seamless metallization structures and methods of manufacture. A structure includes: a contact opening formed in an oxide material and in alignment with an underlying structure; a metal liner lining the sidewalls and bottom of the contact opening, in direct electrical contact with the underlying structure; a conductive liner on the metal liner, within the contact opening; and tungsten fill material on the conductive liner and within the contact opening.

Seamless metallization contacts

The present invention relates generally to forming interconnects over contacts and more particularly, to a method and structure for filling interconnect trenches with a sacrificial filler material before removal of a hard mask layer to protect the liners of the contacts from damage during the removal process. A method is disclosed that may include: filling an opening in a dielectric layer above a contact and a contact liner with a sacrificial filler material, such that the contact liner is completely covered by the sacrificial filler material; removing a hard mask layer used to pattern and form the opening; and removing the sacrificial filler material from the opening selective to the dielectric layer, the contact liner, and the contact to form an interconnect trench.

Hardmask removal for copper interconnects with tungsten contacts by chemical mechanical polishing

A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Doping of copper wiring structures in back end of line processing

A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module.

Post metal chemical-mechanical planarization cleaning process

A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Method of repairing probe pads

Processes and apparatuses are disclosed for detecting and characterizing SiCOH-based dielectric materials during integrated circuit fabrication. The processes generally include chromatographically analyzing a fluid stream generated during a process employed for device fabrication, e.g., during a wet strip, a chemical mechanical planarization process and the like.

Detection and characterization of SiCOH-based dielectric materials during device fabrication

The present invention is an apparatus and method for extending the life of abrasive disks used in the conditioning of polishing pads used in chemical mechanical planarization (CMP) of polishing pads used to polish and/or planarize the surfaces of semiconductor wafers during the production of integrated circuits. The invention consists of the a disk comprising a plurality of abrasive segments, each of which is fixed in tangential and radial relationship to one another about the common axis of rotation of the conditioning disk. Means are provided for movement of the abrasive segments, individually or in sets, into or out of the plane of the active abrasive surface of the conditioning disk according to the present invention.

Extended life conditioning disk

An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

Chemical planarization performance for copper/low-k interconnect structures

A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

Maintaining uniform CMP hard mask thickness

Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Selective capping of copper wiring

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Hopewell Junction, NY, United States of America

Wei-Tsu Tseng