Csmc Technologies Fab2 Co., Ltd.

Southeast University

Jiangsu Electric Power Research Institute Co., Ltd.

State Grid Jiangsu Electric Power Co., Ltd. Research Institute

State Grid Corporation of China

Csmc Technologies Fab1 Co., Ltd.

State Grid Jiangsu Electric Power Company

Wei Su

Longxing Shi

Weifeng Sun

Hao Wang

Shen Xu

Jinyu Xiao

Sen Zhang

Jian Liu

Feng Lin

Jinggang Yang

Yubo Yuan

Shu Chen

Changfeng Xia

Xinwei Zhang

Lei Gao

Mingming Shi

Xiaodong Yuan

Shuyi Zhuang

Tiankui Sun

Xiaolong Xiao

Wei Dong Wang

Yan Gu

Qinsong Qian

Kun Yang

Qi Liu

Peng Li

Qifeng Huang

Qun Li

Xin Fang

Yunlong Jiang

Minggang Chen

Jianhua Qin

Ruihuang Liu

Shengyou Xu

Jiahao Guo

Meihan Guo

Chengjian Fan

Xinyao Si

Liguo Liu

Rui Zhong

Mingshu Zhang

Rongrong Tao

Boyong He

Chenqing Wang

Disclosed is an electrical topology of an integrated DC charging station and an operation control method. The electrical topology comprises a supply side DC bus, K discrete charging pile units and a mutual aid total DC bus; each charging pile unit comprises an input DC bus, a mutual aid sub-DC bus, an output DC bus, N isolation branches, a non-isolation DC/DC module and an output terminal, the input DC bus is connected to the supply side DC bus, and the mutual aid sub-DC bus of each charging pile unit is connected to the mutual aid total DC bus; the isolation branch comprises an output branch and a mutual aid branch; and when all the output branches of one charging pile unit are started and the output power cannot meet the required power, the mutual aid branches of other charging pile units are started to meet the required power.

Electrical topology of integrated dc charging station and operation control method thereof

An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.

Deadtime automatic-optimization system for flyback power supply having primary-side feedback in CCM, control system and method for flyback power supply having primary-side feedback in CCM

Provided is a dynamic control method that turns off a primary-side switching transistor when an output voltage exceeds an upper limit, and control the switching of a secondary-side synchronous rectification transistor with a fixed cycle and a fixed duty cycle. During the time that the synchronous rectification transistor is turned on, the energy of a load capacitor at the output end is extracted to the primary side, which causes the output voltage to drop rapidly and the overshoot voltage to decrease greatly.

Flyback switching power supply, control system thereof and control method therefor

Disclosed is a low-voltage DC power distribution fast switching device. The device includes a positive output terminal electrically connected to a positive pole of a load, and no less than two switching circuits connected in parallel with each other; the switching circuit includes a positive input terminal electrically connected to a positive pole of common negative power supplies, a supplementary diode cluster composed of no less than one diode connected in series, and a thyristor connected between the positive input terminal and the positive output terminal; the positive input terminal is electrically connected to an anode of the supplementary diode cluster and an anode of the thyristor, and the positive output terminal is electrically connected to a cathode of the complementary diode cluster and a cathode of the thyristor.

Low-voltage DC power distribution fast switching device

A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.

Method for reducing noise of a switched reluctance motor based on adjusting a PWM carrier frequency

A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a critical value Tset, calculating a time interval Ttap between adjacent zero points in the current connection time, outputting a shutdown signal at the zero points, and comparing the time interval Ttap with the preset critical value Tset; when Ttap&#x3e;Tset, controlling the current shutdown time to be less than the shutdown time of the preceding cycle and outputting a start signal; when Ttap=0, controlling the current shutdown time to be greater than the shutdown time of the preceding cycle and outputting a start signal; and when 0&#x3c;Ttap&#x3c;=Tset, controlling the current shutdown time to be the same as the shutdown time of the preceding switch cycle and outputting a start signal.

Method for improving conversion efficiency of CCM mode of flyback resonant switch power supply

A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage Vof the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.

Control system for synchronous rectifying transistor of LLC converter

A lateral insulated gate bipolar transistor, comprising: a substrate (), having a first conductivity type; an insulating layer (), formed on the substrate (); an epitaxial layer (), having a second conductivity type and formed on the insulating layer (); a field oxide layer (), formed on the epitaxial layer (); a first well (), having the first conductivity type; a plurality of gate trench structures (); second source doped regions (), having the second conductivity type; first source doped regions (), having the first conductivity type; a second well (), having the second conductivity type; a first drain doped region (), having the first conductivity type and formed on a surface layer of the second well (); gate lead-out ends (); a source lead-out end (); a drain lead-out end ().

Lateral insulated gate bipolar transistor

A parallel plate capacitor includes a first polar plate (), and a second polar plate disposed opposite to the first polar plate (). The parallel plate capacitor further includes at least a pair of sensitive units disposed on a substrate forming the first polar plate (); the sensitive units includes sensitive elements () and element connecting arms () connecting the sensitive elements () to the first polar plate (). The parallel plate capacitor further includes anchoring bases () disposed on a substrate where the second polar plate is located; the anchoring bases () are connected to the element connecting arms () via cantilever beams (); each element connecting arm () is connected to at least two anchoring bases (), which are symmetric with respect to the element connecting arm. The parallel plate capacitor is more likely to be influenced by an external factor, thus being more likely to experience capacitance change. An acceleration sensor including the parallel plate capacitor is also provided.

Parallel plate capacitor and acceleration sensor comprising same

A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wand Wrespectively, W=d/0.71, and W=d/0.71, where dis the maximum wet etching depth to be monitored, and dis the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.

Monitoring structure and monitoring method for silicon wet etching depth

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Wei Su