Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Shuo Ho

Tsung-Yu Chiang

Kuang-Hsin Chen

Chia-Ming Chang

Yen-Ming Peng

Jyun-Ming Lin

Max Liu

Chrong-Jung Lin

Ya-Chin King

Chia-Chun Liao

Tzong-Sheng Chang

An-Lun Lo

Chang-Yin Chen

Bor-Zen Tien

Chai-Wei Chang

Cheng-Chien Li

Huang-Chao Chang

Wei-Zhe Jhang

The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

Gate structure and method with enhanced gate contact and threshold voltage

A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.

FinFET devices having gate stacks with protruding parts and method of forming the same

Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.

Gate structures for semiconductor devices

Gate structures with various widths and method for forming the same

Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.

Semiconductor device and method of fabricating the same

A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation between the first active region and the second active region over the substrate; disposing an inter-level dielectric (ILD) over the substrate; forming a first gate extended over the first active region, the isolation and the second active region; and forming a second gate over the first active region and the second active region, wherein the second gate includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

Metal gate structure and manufacturing method thereof

A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack, which are positioned over a semiconductor substrate and spaced apart from each other. The method includes removing portions of the semiconductor substrate to form a first recess, a second recess, and a third recess in the semiconductor substrate. The method includes forming a first doped structure, a second doped structure, and an isolation structure in the first recess, the second recess, and the third recess respectively. The first gate stack, the second gate stack, the first doped structure, and the second doped structure together form a memory cell. The isolation structure is wider and thinner than the second doped structure. A top surface of the isolation structure has a fourth recess.

Method for forming semiconductor device structure

A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with an insulating layer formed thereon. The method includes forming a gate dielectric layer in the first opening and the second opening. The method includes forming a film over the gate dielectric layer. The method includes forming a first work function metal layer in the first opening. The method includes depositing a second work function metal layer in the first opening and the second opening and in direct contact with the first work function metal layer in the first opening and the film in the second opening. A first deposition rate of the second work function metal layer over the first work function metal layer is greater than a second deposition rate of the second work function metal layer over the film.

Method of manufacturing semiconductor device

A semiconductor device includes a transistor and a contact pad over a substrate. The transistor includes a high-k dielectric layer, a work function metal layer, a metal gate, two spacers, a metal compound, an insulator and a doped region. The high-k dielectric layer is over the substrate. The work function metal layer is over the high-k dielectric layer. The metal gate is over the work function metal layer. The two spacers sandwich the work function metal layer and the metal gate. The metal compound is over inner walls of the two spacers and over the top surface of the work function metal layer and the metal gate. The insulator covers the metal compound. The doped region is in the substrate. The contact pad is electrically connected to the metal gate.

Modified self-aligned contact process and semiconductor device

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material.

Semiconductor device structure and method for forming the same

A semiconductor structure includes a substrate including a first active region, a second active region and an isolation disposed between the first active region and the second active region; a plurality of gates disposed over the substrate and including a first gate extended over the first active region, the isolation and the second active region, and a second gate over the first active region and the second active region; and an inter-level dielectric (ILD) disposed over the substrate and surrounding the plurality of gates, wherein the second gate is configured not to conduct current flow and includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

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Taipei, Taiwan

Wei-Shuo Ho