Vanguard International Semiconductor Corporation

Wei-Shung Chen

Jui-Lung Chen

Chia-Chiuan Chang

Yi-Hsun Chung

Shao-Chang Huang

Chih-Cherng Liao

Yeh-Ning Jou

Chieh-Yao Chuang

Hsien-Feng Liao

Jia-Rong Yeh

Ching-Wen Chen

Pang-Chuan Chen

Yi-Han Wu

An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.

Integrated circuit and electrostatic discharge protection circuit thereof

A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure.

Burn-in methods for static random access memories and chips

A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit provides the source voltage to the memory units. When the memory unit is in a writing status, the source voltage is the first power voltage. When the memory unit is in a reading status, the source voltage is the second power voltage. The second power voltage equals to the first power voltage subtracted by a specific voltage for avoiding rewriting error.

Memory system

Growing community of inventors

Hsinchu County, Taiwan

Wei-Shung Chen