Synopsys, Inc.

Synopsys Taiwan Co., Ltd.

Wei-Shun Chuang

Sheng-Hsiung Chen

Fong-Yuan Chang

Hsian-Ho Chang

Ruey-Shi Rau

Chiu-Yu Ku

Chia-Wei Hsu

A method is disclosed including analyzing a layout netlist including a first set of nodes against a schematic netlist including a second set of nodes. Each node of the first and second sets of nodes is assigned a matching type for identifying matching nodes between the first and second sets of nodes. The method includes determining one or more unmatched nodes between the first set of nodes and the second set of nodes based on the matching type. The method includes generating a convergence graph comprising nodes of the first set of nodes that have a corresponding matching node in the second set of nodes based on the matching type, and the one or more unmatched nodes.

Layout-versus-schematic (LVS) debugging and error diagnosis via type of graph matching

A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values based on the first value, according to a graph coloring algorithm, until reaching a third node of the first graph and a corresponding fourth node of the second graph that are assigned different values. The LVS tool generates an output identifying the third node and the fourth node as a root cause of the detected mismatch.

Identifying root cause of layout versus schematic errors

A computer implemented method for routing a net includes selecting, using one or more computer systems, a first spine routing track from a first multitude of routing tracks in accordance with a first cost function, and further in accordance with data associated with the net and the first multitude of routing tracks. The method further includes generating, using one or more computer systems, a first spine wire on the selected first spine routing track.

Multiple level spine routing

Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets.

A computer implemented method for routing a net includes generating, using one or more computer systems, a first wire associated with the net in accordance with data associated with the net including a multitude of pins and partitioning, using the one or more computer systems, the multitude of pins into at least a first group of pins in accordance with a first cost function. The method further includes connecting, using the one or more computer systems, a second wire associated with the first group of pins to the first wire, and connecting, using the one or more computer systems, a third wire from a pin of the first group of pins to the second wire.

Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net.

Growing community of inventors

Hsinchu, Taiwan

Wei-Shun Chuang