Globalfoundries Singapore Pte. Ltd.

Alsephina Innovations Inc.

Wei Shao

Juan Boon Tan

Wanbing Yi

Fan Zhang

Wei Liu

Vish Srinivasan

Yi Jiang

Wei Lu

Soh Yun Siah

Yeow Kheng Lim

Wuping Liu

Mahesh Bhatkar

Shunqiang Gong

Daxiang Wang

Chao Zhu

Gong Shun Qiang

A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.

Stitched devices

Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

Integrated magnetic random access memory with logic device

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.

Integrated circuits having device contacts and methods for fabricating the same

An integrated circuit includes a copper hillock-detecting structure. The copper hillock-detecting structure includes a copper metallization layer and an intermediate plate structure spaced apart from adjacent to the copper metallization layer. The intermediate plate structure includes a conducting material plate. The intermediate plate structure further includes a plurality of conductive vias that are electrically and physically connected with the conducting material plate. The copper hillock-detecting structure further includes a sensing plate adjacent to the intermediate plate and electrically and physically connected with the plurality of vias such that the vias are disposed between the intermediate plate and the sensing plate.

Integrated circuits with copper hillock-detecting structures and methods for detecting copper hillocks using the same

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposite within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact.

Methods for fabricating integrated circuits having device contacts

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes fabricating a crack-stop structure that extends through a plurality of metallization layers above a semiconductor substrate. The plurality of metallization layers includes a first metallization layer and a second metallization layer that overlies the first metallization layer. Fabricating the crack-stop structure includes forming a first via-bar overlying and coupled to a first metal line of the first metallization layer that is disposed in a first ILD layer of dielectric material. The first via-bar is disposed in a second ILD layer of dielectric material and has a first width. A second metal line of the second metallization layer that is in the second ILD layer is formed overlying and coupled to the first via-bar. The second metal line has a second width that is from about 1 to about 5 times the first width.

Integrated circuits having crack-stop structures and methods for fabricating the same

Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include Mto Mmetal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level Mincludes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having M. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between Mand its adjacent underlying metal level M.

Semiconductor device and method of forming thereof

A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.

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Singapore, Singapore

Wei Shao