Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Ren Wang

Tze-Liang Lee

Ching-Yu Chang

Shing-Chyang Pan

Jung-Hau Shiu

Jen Hung Wang

Wan-Lin Tsai

Hsiu-Wen Hsueh

Cai-Ling Wu

Po-Hsiang Huang

Chii-Ping Chen

Jen-Hung Wang

In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.

Self-aligned scheme for semiconductor device and method of forming the same

A semiconductor device includes a first conductive feature, a first dielectric layer over the first conductive feature, a second conductive feature extending through the first dielectric layer, an air gap between the first dielectric layer and the second conductive feature, and an etch stop layer over the second conductive feature and the first dielectric layer. The etch stop layer covers the air gap, and the air gap extends above a bottommost surface of the etch stop layer.

Interconnect structure and method of forming the same

An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.

Interconnect structures and methods of forming the same

An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.

Semiconductor device and method

A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.

Semiconductor structure and manufacturing method thereof

Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

Patterning methods for semiconductor devices

Embodiments provide a patterning process. A photoresist layer is patterned. At least portions of the photoresist layer are converted from an organic material to an inorganic material by a deposition process of a metal oxide. All or some of the patterned photoresist layer may be converted to a carbon-metal-oxide. A metal oxide crust may be formed over the patterned photoresist layer. After conversion, the patterned photoresist layer is used as an etch mask to etch an underlying layer.

Growing community of inventors

Taipei, Taiwan

Wei-Ren Wang