Raymx Microelectronics Corp.

Realtek Semiconductor Inc.

Wei-Ren Hsu

Yen-Chung Chen

Jiunn-Jong Pan

Chih-Yen Chen

Chih-Ching Chien

Ming-Yuh Yeh

Li-Chun Huang

Yi-Ting Wei

Yufeng Zhou

Fu-Hsin Chen

Han-Ting Tsai

Wen-Hsin Chang

A storage device includes a controller and a memory. A method of storage space management for the storage device is executed to perform steps as below. The controller calculates an expectedly used capacity and an effective capacity of the memory. The controller determines whether blocks of the memory include one or more blocks that are non-bad blocks and are prohibited from reading/writing. When the one or more blocks are determined to be non-bad blocks and to be prohibited from reading/writing, the controller marks each of the one or more blocks as a restricted block other than a bad block, thereby maintaining the effective capacity to be unchanged. The controller compares difference of the effective capacity and a total capacity of the one or more blocks that are marked as the restricted block to the expectedly used capacity to determine whether to prohibit programming to the memory.

Method of storage space management for improving endurance of storage devices

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

Data processing method and memory controller utilizing the same

The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.

Memory controller and method having predictive buffering of address mapping table

An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.

Data storage device and operation method of the same

The present invention provides a flash memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the flash memory controller, the AI module receives data from a host device, and determines if the data is important data or unimportant data to generate a determination result. The microprocessor is configured to write the data into a flash memory module according to the determination result, wherein the flash memory module comprises a plurality of first blocks and a plurality of second blocks, and quantity of bits stored in each memory cell within the first blocks is lower than quantity of bits stored in each memory cell within the second blocks. When the determination result indicates that the data is the important data, the microprocessor only stores the data into at least one of the first blocks.

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Taipei, Taiwan

Wei-Ren Hsu