Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Tsinghua University

Wei-Ren Chen

Hui-Zhong Zhuang

Jerry Chang Jui Kao

Huang-Yu Chen

Yung-Chen Chien

Wei-Ling Chang

Cheng-Yu Lin

Li-Chun Tien

Chih-Liang Chen

Lee-Chung Lu

Chung-Hsing Wang

Stefan Rusu

Wei-Chung Wang

Chi-Hung Huang

Po-Chia Lai

Po-Chi Sung

Ming-Chang Kuo

Lin-Chieh Wei

Guan-Ting Lai

An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.

Integrated circuit device and method

An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.

Semiconductor structure and layout method of a semiconductor structure

A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Multiple fin count layout, method, system, and device

A display device includes a first substrate, first signal lines, second signal lines, active elements, pixel electrodes, a second substrate, a black matrix, a first spacer, and a second spacer. The active elements are electrically connected with the first signal lines and the second signal lines. The black matrix includes first portions and second portions. The first portions overlap the first signal lines. The second portions overlap the second signal lines. The first spacer overlaps a source and a drain of one of the active elements. The second spacer overlaps a source and a drain of another one of the active elements. The shortest distance between the center of the first spacer and the center line of the closest one of the first portions is different from the shortest distance between the center of the second spacer and the center line of the closest one of the first portions.

Display device

An apparatus for quantifying unknown stress and residual stress of a material to be tested, the material being a birefringent or temporary birefringent material, which includes a light source, a polarizer in front of the light source for converting a light beam from the light source into a beam with linear polarization, a first quarter-wave plate in front of the polarizer for generating circular polarization, a standard material, a second quarter-wave plate, an analyzer, a loading unit, a spectrometer for obtaining transmissivity spectrum of the standard material under the wavelength of the light source and a detecting module connected to the spectrometer to have the transmissivity spectrum of the material to be tested and consequently a stress quantifying formula for the standard material.

Apparatus for quantifying unknown stress and residual stress of a material and method thereof

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Hsinchu, Taiwan

Wei-Ren Chen