Vanguard International Semiconductor Corporation

Nan Ya Technology Corporation

Wei-Ray Lin

Fu-Liang Yang

Erik S Jeng

Ming-Hong Kuo

Hsu-Li Cheng

Chung-Ju Lee

Liang-Gi Yao

Hsien-Wen Liu

Bi-Ling Chen

Yue-Feng Chen

Yeur-Luen Tu

Bih-Tiao Lin

Yu-Chun Ho

Chien-Sheng Hsieh

Li-Yeat Chen

Bor-Ru Sheu

A method for producing capacitor-node contact plugs of a dynamic random access memory, comprising: providing a semiconductor substrate; forming at least one gate structure separated by a first isolation layer as a word line, and forming a source region and a drain region next to the word line; forming a second isolation layer to cover the first isolation layer, word line, source region, and drain region; forming a first landing pad, which passes through the second isolation layer and couples to the source region, wherein the first landing pad is offset a given distance along the word line; forming a third isolation layer to cover the second isolation layer and the first landing pad; forming a second landing pad coupled to the drain region through the second isolation layer and the third isolation layer; forming at least one bit line separated by a fourth isolation layer along the vertical direction to the word line, wherein the at least one bit line is coupled to the second landing pad; forming a fifth isolation layer to cover the at least one bit line separated by the fourth isolation layer; and forming a capacitor-node contact plug, which is coupled to the side wall and a part of the top of the first landing pad through the fifth isolation layer, the third isolation layer, and the second isolation layer.

Methods for producing capacitor-node contact plugs of dynamic random-access memory

A method for forming planarized isolation using a nitride hard mask and two CMP steps is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride and pad oxide layers are etched through where they are not covered by a mask to provide at least one wide opening and at least one narrow opening where the surface of the substrate is exposed. Trenches are etched into the substrate where it is exposed. An oxide layer is deposited overlying the first nitride layer and within the trenches completely filling the narrow trench wherein a trough is formed over the wide trench. A second nitride layer is deposited over the oxide layer. The second nitride layer is polished away with a polish stop at the oxide layer whereby the second nitride layer is removed except: where it lies within the trough. The oxide layer is etched back where it is not covered by the second nitride layer wherein the oxide layer is planarized except where the oxide layer underlies the second nitride layer. The second nitride layer is removed within the trough whereby oxide horns forming the trough extend vertically upward from the planarized oxide surface. Thereafter, the oxide layer is polished away with a polish stop at the first nitride layer whereby the oxide horns are removed. The first nitride and the pad oxide layers are removed completing formation of the shallow trench isolation.

Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMP

A method divides the formation of the contact plug connecting a source/drain region in the peripheral circuit area into two steps, wherein the capacitor can be fabricated at the same time so as to save one mask. Besides, at each step of forming the contact plug with low aspect ratio, a CVD method is utilized to uniformly deposited a barrier layer on the contact window and completely fill the contact window. This can thoroughly eliminate the defects found in the prior art. Consequently, the simplified process can reduce the manufacturing period time and the production cost.

Method of forming a capacitor and a contact plug

A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer. Chemical-mechanical polishing is performed. Successive oxide etch, nitride etch and oxide etch steps are performed defining elevated trench isolation regions fully planarized with the first gate electrode layer. A silicide layer, a dielectric layer and a top nitride layer are formed. The top nitride layer, the dielectric layer, the silicide layer, the first gate electrode layer and the gate oxide layer are patterned forming gate structures between elevated trench isolation regions and conductive lines on elevated trench isolation regions. Spacers are formed on the sidewalls of the gate structures, the conductive lines and the elevated trench isolation regions. Then, self-aligned contact plugs are formed adjacent to the spacers.

Method of fabricating a self-aligned contact

A method of fabricating a crown capacitor comprises first providing a substrate having a transistor, constituted by at least one diffused region, formed thereon and overlaid by a first insulating layer. Bit lines are formed in the first insulating layer. A first masking layer and a second insulating layer are sequentially formed over the substrate. The second insulating layer, the first masking layer and the first insulating layer are patterned to form a contact hole that exposes the diffused region. A second masking layer is conformally formed and etched back to form masking spacers on the sidewalls of the contact hole. The second insulating layer is removed. A first conductive layer is conformally formed over the first masking layer and extending to the surface of the masking spacers and the bottom of the contact hole. A third insulating layer is formed over the first conductive layer and fills the contact hole. The third insulating layer and the first conductive layer are patterned to the first masking layer leaving portions of the third insulating layer with vertical sidewalls over the contact hole. A second conductive layer is conformally formed and etched back to form conductive spacers on the sidewalls of the third insulating layer. The third insulating layer is removed to expose the conductive spacers and the first conductive layer as a bottom electrode. A capacitor dielectric layer and a top electrode are sequentially formed on the bottom electrode.

Method of fabricating crown capacitor

A process for fabricating a DRAM capacitor structure, in which the capacitor upper plate structure is defined during the formation of bit line contact hole opening, and substrate contact hole opening procedure, eliminating the need for a specific upper plate, photolithographic masking procedure, has been developed. The process features isolating a polysilicon upper plate structure, during an isotropic RIE cycle, also creating an undercut polysilicon region, in the contact holes, which are opened simultaneously during the upper plate definition. Subsequent silicon nitride spacers, on the sides of the contact holes, provides insulation between the polysilicon upper plate structure, and bit line, and substrate contact plug structures, now located in the contact holes. The undercut polysilicon regions, allow the formation of thicker silicon nitride spacers, to be formed in this undercut region.

Method of fabricating a capacitor under bit line DRAM structure using contact hole liners

A method for forming planarized shallow trench isolation is described. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the nitride layer into the semiconductor substrate wherein there are at least one wide trench and at least one narrow trench. A first oxide layer is deposited over the first nitride layer and within the isolation trenches wherein the first oxide layer fills the isolation trenches. A capping nitride layer is deposited overlying the first oxide layer. A second oxide layer is deposited overlying the capping nitride layer. The second oxide layer is polished away wherein the second oxide layer and the capping nitride layer are left only within the wide trench. The first and second oxide layers are dry etched away with an etch stop on the capping nitride layer within the wide trench and the first nitride layer wherein the second oxide layer is completely removed. Thereafter, the first oxide layer is overetched to leave the top surface of the first oxide layer just above the bottom surface of the first nitride layer and the capping nitride layer within the wide trench. The capping nitride layer and the first nitride layer are removed completing the formation of shallow trench isolation regions in the fabrication of an integrated circuit device.

Formation of finely controlled shallow trench isolation for ULSI process

A method for forming self-rounded shallow trench isolation is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is then deposited overlying the pad oxide layer. Isolation trenches are then etched through the nitride and pad oxide layers into the semiconductor substrate. A layer of oxide is then deposited over the said nitride layer and within the isolation trenches. The oxide layer is then polished away through chemical and mechanical polishing wherein the substrate is planarized. The nitride layer is then etched away using a special dry-etch recipe that has a higher etching rate for silicon nitride than oxide. The dry-etch recipe also has a very low etching rate for the silicon substrate. This results in the removal of the nitride layer, rounding the shoulders of the trench and leaving the substrate unaffected. The fabrication of the integrated circuit device is completed.

Methods for shallow trench isolation

A method of planarizing a structure having an interpoly layer is disclosed. The method includes forming an undoped silica glass layer on at least a polysilicon region formed on a semiconductor substrate. Next, a spin-on-glass layer is formed over the undoped silica glass layer. Finally, the spin-on-glass layer is etched back, thereby planarizing the structure having the interpoly layer.

Method of planarizing a structure having an interpoly layer

A method of fabricating a crown capacitor comprising first providing a substrate having a transistor, constituted by at least one diffused region, formed thereon and overlaid by a first insulating layer. Bit lines are formed in the first insulating layer. A first masking layer and a second insulating layer are sequentially formed over the substrate. The second insulating layer, the first masking layer and the first insulating layer are patterned to form a contact hole that exposes the diffused region. A second masking layer is conformally formed and etched back to form masking spacers on the sidewalls of the contact hole. A third insulating layer is formed over the substrate, wherein the third insulating layer fills the contact hole. The second insulating layer and the third insulating layer are selectively removed to expose portions of the first masking layer, the masking spacers and the diffusion areas. A conductive layer is conformally formed over the portions of the first masking layer, the masking spacers and the diffusion areas. A fourth insulating layer is formed over the conductive layer. The fourth insulating layer and the conductive layer are planarized to the third insulating layer. The fourth insulating layer, the third insulating layer, and the second insulating layer are removed to expose the conductive layer as a bottom electrode. A capacitor dielectric layer and a top electrode are sequentially formed on the bottom electrode.

A thin silicon dioxide layer is formed on the substrate to act as a pad layer. Subsequently, a silicon nitride layer is deposited on the pad layer. Trenches are formed in the substrate. The trenches include first trenches and a second trench that has a relatively wide opening compared to the first trenches. An CVD-oxide layer is formed on the silicon nitride layer and refilled into the trenches. A multi-layer is then formed on the CVD-oxide layer. The multi-layer includes alternating PE-nitride layers and PE-oxide layers. Subsequently, a chemical mechanical polishing (CMP) technology is used for removing the multi-layer layer to the surface of the silicon nitride layer.

Method of forming a shallow trench isolation by using PE-oxide and

A method for forming planarized isolation by combining LOCOS and STI isolation processes is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride layer and pad oxide layer are etched through where they are not covered by a mask to provide openings where the surface of the semiconductor substrate is exposed wherein there is at least one wide opening and one narrow opening. A second nitride layer is deposited over the substrate and etched back to leave spacers on the sidewalls of the openings wherein the narrow opening is filled by the spacers. The exposed semiconductor substrate within the wide opening is oxidized wherein a field oxide region is formed within the wide opening. A portion of the first nitride layer and spacers is etched away whereby the semiconductor substrate within the narrow opening is exposed. A trench is etched into the semiconductor substrate where it is exposed within the narrow opening. An oxide layer is deposited overlying the first nitride layer and field oxide region and filling the trench wherein the oxide layer filling the trench forms a shallow trench isolation region. The oxide layer is polished away with a polish stop at the first nitride layer. The first nitride layer, the spacers, and the pad oxide layer are removed, completing formation of both a field oxide region and a shallow trench isolation region in the fabrication of an integrated circuit device.

Method to fabricate isolation by combining locos and shallow trench

A silicon dioxide layer and a silicon nitride layer are formed on the wafer. Subsequently, a plurality of shallow trenches are generated in the wafer. A HDP-CVD oxide having protruding portions is refilled into the trenches and formed on the silicon nitride layer for isolation. A wet etch is performed to etch the HDP-CVD oxide layer such that the corners of the silicon nitride layer formed on the active area will be exposed. A cap silicon nitride layer is then conformally formed on the surface of the oxide layer. Then, a chemical mechanical polishing (CMP) process is used to remove the top of the cap silicon nitride layer, thereby exposing the residual protruding portions of the oxide layer. The residual protruding portions of the oxide layer are next removed. Then, the silicon nitride layer and the cap silicon nitride layer are both removed by conventional methods. Finally, the pad oxide is removed.

Method of making a shallow trench isolation for ULSI formation via

A stacked layer including a first oxide, a nitride layer, a second oxide layer and an oxynitride layer is formed on the top of the first oxide layer. An etching is performed through a photoresist to etch the oxynitride, the second oxide and nitride. Oxide spacers are formed on the side walls of the pattern structure, the oxynitride layer is also removed during the formation of the oxide spacers. Trenches are generated by a dry etching technique. The second oxide and the oxide spacers are removed. Next, a thermal oxidation is performed to rounding the corners of the trench openings. A gap filling material is refilled into the trenches and formed on the nitride. Next, a chemical mechanical polishing (CMP) is used to remove the top of the CVD-oxide and the nitride layer. The residual nitride layer, the CVD-oxide and pad oxide are removed to create trench isolation structures with rounding corners.

Growing community of inventors

Taipei, Taiwan

Wei-Ray Lin