Neomagic Corporation

Marvell International Limited

Sandcraft, Inc.

Faust Communications, LLC

Wei-Ping Lu

Fathy Yassa

Edward T Pak

Tejvansh Singh Soni

Victor Shadan

Yuan-ping Chen

Yaron Serfaty

An edge-triggered flip-flop is provided that includes one or more storage nodes and a pre-charge circuit in communication with the storage circuit. The storage circuit is configured to pre-charge the one or more storage nodes to a pre-determined voltage potential. The storage circuit further includes a first pull-down logic circuit in communication with the storage circuit and separate second pull-down logic circuit in communication with the storage circuit. The first pull-down logic circuit is configured to discharge one or more of the pre-charged storage nodes in response to first input data and the second pull-down logic circuit is configured to discharge one or more of the pre-charged storage nodes in response to second input data.

Edge-triggered flip-flop

An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.

Pipelined carry-lookahead generation for a fast incrementer

An associative processor uses a content-addressable memory (CAM) array to operate on data. The array has several CAM banks that store data in CAM memory cells. Each CAM bank has a register file that stores compare data that drives compare bit lines to the CAM cells, which activate row-match signals for rows with matching data. Each CAM bank has a register file with copies of compare data for all CAM banks. An index value identifies which of the compare registers drives the bank's compare bit lines. When a bank-swap instruction is executed, the index values of two banks are swapped, causing the compare data to be used for a different CAM bank. The physical data in the CAM banks is not swapped, but the compare data used for comparisons is swapped. Since the register files contain all banks' compare data, the compare data does not have to be physically moved.

Hardware-assisted fast bank-swap in a content-addressable-memory (CAM) processor

A method and a device for maintaining logic state stored in a storage device are described. For one embodiment, the device precharges at least two complimentary nodes in a storage device during the precharge cycle. During the evaluation cycle, the device receives an input data. After receipt of the input data, device stores at least one logic state at a storage node according to the input data. The device includes at least one conducting path to limit one store per each evaluation stage.

Growing community of inventors

Saratoga, CA, United States of America

Wei-Ping Lu