Silergy Semiconductor Technology (hangzhou) Ltd

Monolithic Power Systems, Inc.

Intel Corporation

Silergy Technology

Cisco Technology, Inc.

Linear Technology Corporation

United Microelectronics Corp.

Facebook, Inc.

Intersil Americas Inc.

Curasen Therapeutics, Inc.

Hangzhou Silergy Semiconductor Technology Ltd

Other

Sk Hynix Nand Product Solutions Corp.

Voxeo Corporation

Vpt, Inc.

Wei P Chen

Rajat Agarwal

Xiaoru Xu

Kaiwei Yao

Yuancheng Ren

James Copland Moyer

Jing Ling

Zhiyu Liu

Xiaopu Zhu

Sangsun Kim

Shenglun Chen

Jason Scott Goecke

Peng Xu

Daniel W Liu

Jose Maria De Castro, Jr

Kuljit Singh Bains

Chen Zhao

Yen-Cheng Liu

Jiaxin Yu

Bill Nale

Junming Zhang

Huiqiang Chen

Theodros Yigzaw

John G Holm

Suresh S Chittor

Yunlong Han

Andrew M Rudoff

David Scott Carter

Paul T Ueunten

Jose De Castro

Chet R Douglas

Guojia Liu

Andy M Rudoff

XiaoChun Tan

Michael Grimm

Neil Stratford

Anthony P Ford

Tiffany J Kasanicky

Sai Prashanth Muralidhara

Kevin Chatow

Michael Cervantes

Pubing Zhang

Stefan Rusu

Krishnakanth Venkata Sistla

Min Huang

Mark A Schmisseur

James A McCall

George Vergis

Mahesh S Natu

Gustavo James Mehas

Jianxin Wang

Kevin X Zhang

Qiukai Huang

Wei Wu

Ashok Raj

Sarathy Jayakumar

Wang Zhang

Fatih Hamzaoglu

Eric X Yang

Alaa R Alameldeen

Stephen R Van Doren

Xin Zhang

Xiaochun Tan

Larisa Novakovsky

Yongjiang Bai

Deep K Buch

Gwilym Francis Luff

Lei Du

Zhiliang Hu

Liangwei Sun

James Earl McCormick, Jr

Eswaramoorthi Nallusamy

Hongbin Lai

Anuj Kumar

David Meng

Bruce Lee Inn

Peter John Mole

Sreenivas Mandava

Douglas Heymann

Gunjan H Pandya

Anand K Enamandram

Vivek Joy Kozhikkottu

Kjersten E Criss

Shuai Cheng

Dhrubajyoti Borthakur

Robert A Branch

Jie Yao

Guichao Hua

Tsung-yung Jonathan Chang

Xiangdong Yang

Kerry Vander Kamp

Xiaopeng Dong

Nishant Singh

Sharada Venkateswaran

Tung Chi Chang

Daniel M Sable

Simon Tsai

Hsing-Min Chen

Eric Rasmussen

Monam Agarwal

A system can dynamically migrate memory pages from near memory to far memory during runtime. A system basic input output system (BIOS) can program a first memory address space of size P and a second memory address space of size P to a near memory (NM) space of size (N) and a far memory (FM) space of size (M), where P equals N+M. For the first memory address space, the OS can manage the NM space and the FM space as a flat memory space with an address space of size P available. For the second memory address space, the OS can manage the NM space as a NM cache for FM, with an address space of size M available.

Dynamic multilevel memory system

A system includes a multilevel memory such as a two level memory (2LM), where a first level memory acts as a cache for the second level memory. A memory controller or cache controller can detect a cache miss in the first level memory for a request for data. Instead of automatically performing a swap, the controller can determine whether to perform a swap based on a swap policy assigned to a memory region associated with the address of the requested data.

Selective fill for logical control over hardware multilevel memory

A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N−M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.

Distribution of error checking and correction (ECC) bits to allocate ECC bits for metadata

A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and predicted cold pages in second level main memory. The cache line granularity movement is performed in a 'swap' manner, that is, a hot cache line in the second level main memory is swapped with a cold cache line in first level main memory because data is stored in either first level main memory or second level main memory not in both first level main memory and second level main memory.

Two-level main memory hierarchy management

A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow without needing to send another read to the memory for the data. The read data is stored in a read data buffer (RDB) at the memory controller when the read data is received from memory. The memory controller has an error detection path from the RDB to the host and an error correction path. Read data that has no errors can be sent directly to the host. Instead of flushing the RDB in response to the error detection, the memory controller executes a retry flow, where the RDB provides the read data to the error correction path for error correction.

Fast memory ECC error correction

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Accessing a memory using index offset information

An embodiment of an electronic memory apparatus may include storage media, and logic communicatively coupled to the storage media, the logic to determine if a mode is set to one of a first mode or a second mode, perform a soft post package repair in the first mode, and undo the soft post package repair in the second mode. Other embodiments are disclosed and claimed.

Undo and redo of soft post package repair

A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

Memory system, computing system, and methods thereof for cache invalidation with dummy address space

An embodiment of a memory controller device includes technology to control access to a multi-level memory including at least a first level memory and a second level memory, provide direct access to the first level memory based on a system memory address, cache accesses to the second level memory in a second portion of the first level memory, and address a memory space with a total memory capacity which includes a first capacity of the first portion of the first level memory plus a second capacity of the second level memory. Other embodiments are disclosed and claimed.

Memory utilized as both system memory and near memory

In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

Hardware unit for reverse translation in a processor

Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.

Method and apparatus to reduce power consumption for refresh of memory devices on a memory module

A multi-input single-output DC-DC converter can include: a plurality of input circuits and an output circuit, where each input circuit includes a first switch, and one terminal of each of the input circuits is coupled to an input source, and the other terminal of the input circuit is coupled to the output circuit; and a control circuit configured to control operation periods of each input circuit in one switching period, in order to achieve power distribution and reach requirements for input currents of the input circuit and an output signal of the output circuit.

Multi-input single-output DC-DC converter, control circuit and control method thereof

Techniques for database versioning are described. In one embodiment, an apparatus may comprise a database change management component operative to compare a developer table to a reference table to determine a database change set, wherein both the developer table and the reference table are based on a target table; a database conflict management component operative to compare the database change set to the target table to determine a conflicting change set; and a user interface component operative to display the conflicting change set where the conflicting change set comprises one or more conflicting changes; and indicate a conflict-free change set where the conflicting change set is empty. Other embodiments are described and claimed.

Techniques for database versioning

The present disclosure is directed to chemical compounds and to the use of such compounds in the treatment of diseases associated with an adrenergic receptor.

Beta adrenergic agonist and methods of using the same

Growing community of inventors

Portland, OR, United States of America

Wei P Chen